Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A dielectric layer is disposed over an upper surface of the bottom electrode. A top electrode is disposed over an upper surface of the dielectric layer and is in direct electrical contact with a lower surface of the upper metal layer.

Abstract: A semiconductor device includes: a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate; a first insulating plate disposed over the first conductive plate and the second conductive plate; a third conductive plate disposed over the first insulating plate; a second insulating plate disposed over the third conductive plate; a fourth conductive plate disposed over the second insulating plate; a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the fourth conductive plate and the first conductive plate; and a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate, wherein the second conductive via is electrically coupled to the third conductive plate and the second conductive plate.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect disposed within a dielectric structure over a substrate. A memory device includes a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the lower interconnect. A sidewall spacer includes an interior sidewall that continuously extends from along an outermost sidewall of the top electrode to below an outermost sidewall of the bottom electrode. The sidewall spacer further includes an outermost sidewall that extends from a bottom surface of the sidewall spacer to above a top of the bottom electrode.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source/drain region arranged within a substrate. A first select gate is arranged over the substrate, and a first memory gate is arranged over the substrate and separated from the source/drain region by the first select gate. An inter-gate dielectric structure is arranged between the first memory gate and the first select gate. The inter-gate dielectric structure extends under the first memory gate. A height of the inter-gate dielectric structure decreases along a direction extending from the first select gate to the first memory gate.

Abstract: A deep trench is formed in a substrate, and a layer stack including at least three metallic electrode plates interlaced with at least two node dielectric layers is formed in, and over, the deep trench. A contact-level dielectric material layer over the layer stack, and contact via cavities are formed therethrough. The depths of the contact via cavities are differentiated by selectively increasing the depth of a respective subset of the contact via cavities by performing at least twice a combination of processing steps that includes an etch mask formation process and an etch process. A combination of a dielectric contact via liner and a plate contact via structure can be formed within each of the contact via cavities. Plate contact via structures that extend through any metallic electrode plate can be electrically isolated from such a metallic electrode plate by a respective dielectric contact via liner.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: A method of forming a semiconductor device includes: depositing a first conductive plate and a second conductive plate adjacent to the first conductive plate; depositing a first insulating plate on the first conductive plate and the second conductive plate; depositing a third conductive plate on the first insulating plate; depositing a second insulating plate on the third conductive plate; forming a fourth conductive plate on the second insulating plate; forming a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate; and forming a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a transistor layer, a memory region over the transistor layer, and a logic region adjacent to the memory region. The memory region includes a first Nth metal line, a magnetic tunneling junction (MTJ) over the first Nth metal line, a cap over the MTJ, a first stop layer on the cap, and a first (N+1)th metal via over the MTJ. The first (N+1)th metal via is laterally surrounded by the cap and the first stop layer. The logic region includes a second Nth metal line, a second stop layer over an (N+1)th metal line, and a second (N+1)th metal via over the (N+1)th metal line. N is an integer greater than or equal to 1.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.

Abstract: A memory device with hard mask insulator and its manufacturing methods are provided. In some embodiments, the memory device includes a memory cell stack disposed over a substrate. The memory cell stack includes a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is disposed over the top electrode layer, and a first metal hard masking layer disposed over the first insulating layer.

Abstract: A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC), including a bottom electrode overlying an interconnect structure disposed within a lower inter-level dielectric (ILD) layer, a top electrode over the bottom electrode, a data storage structure between the top electrode from the bottom electrode, a conductive barrier layer directly overlying the interconnect structure, and a bottom electrode via (BEVA) vertically separating and contacting a bottom surface of the bottom electrode and a top surface of the conductive barrier layer. A maximum width of the BEVA is less than a width of the data storage structure.

Abstract: The present disclosure provides a semiconductor structure and a method for fabricating semiconductor structure. The semiconductor structure includes a first device, configured to be a complementary metal oxide semiconductor device, wherein the first device includes a substrate, a multi-layer structure disposed on the substrate, a first hole, defined between a first end with a first circumference and a second end with a second circumference, a second hole, aligned to the first hole and defined between the second end and a third end with a third circumference, wherein the third circumference is larger than the first circumference and the second circumference, and a second device, configured to be a micro-electro mechanical system device and bonded to the first device, wherein a first chamber is between the first device and the second device, and the first end links with the first chamber, and a sealing object configured to seal the second hole.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a first dielectric layer having a first region and a second region. A bottom electrode is at least partially arranged within the first region of the first dielectric layer. A memory element is over the bottom electrode and a top electrode is over the memory element. A second dielectric layer is over at least the first region of the first dielectric layer. The second dielectric layer surrounds the memory element and at least a part of the top electrode. A third dielectric layer is over the second region of the first dielectric layer and laterally adjacent to the second dielectric layer. A conductive interconnect is in the third dielectric layer and the second region of the first dielectric layer. The first dielectric layer has a different non-zero thickness within the first region than within the second region.

Abstract: Some embodiments pertain to a semiconductor device. The semiconductor device includes a semiconductor substrate including a trench extending downward into an upper surface of the semiconductor substrate. The trench includes a bottom surface and a plurality of scallops along sidewalls of the trench. An oxide layer lines the bottom surface and the sidewalls of the trench. The oxide layer has varying thicknesses along the sidewalls of the trench at different depths. The varying thicknesses step down at discrete increments as a depth into the trench increases.

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: A semiconductor structure includes: a first device; a second device contacted with the first device, wherein a chamber is formed between the first device and the second device; a first hole disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference; a second hole disposed in the second device and aligned to the first hole; and a sealing object for sealing the second hole. The first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.