Patents by Inventor Shih-Cheng Huang

Shih-Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190304909
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
  • Patent number: 10410684
    Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: September 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu
  • Patent number: 10381306
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 13, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
  • Patent number: 10367517
    Abstract: An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 30, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Cheng Wu, Shih-Hsiung Huang
  • Publication number: 20190221238
    Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.
    Type: Application
    Filed: February 21, 2018
    Publication date: July 18, 2019
    Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu
  • Publication number: 20190201599
    Abstract: The present invention relates to a negative pressure wound therapy device, system and method. The negative pressure wound therapy device is connected with a dressing, and comprises a housing, a control circuit board, a pump, and an aspiration conduit. The pump generates negative pressure. The pump may comprise a voltage-actuated deformation element (such as piezoelectric vibration element) to push fluid from an aspiration end to a discharge end. The aspiration conduit has a pump end and a dressing end. The pump end is fluidly connected to the aspiration end of the pump, and the dressing end is fluidly connected to the dressing used for covering a wound. The control circuit board is disposed in the housing, controls the pump to generate the negative pressure in the aspiration conduit, and applies negative pressure to the wound covered by the dressing via the aspiration conduit.
    Type: Application
    Filed: December 6, 2018
    Publication date: July 4, 2019
    Inventors: PO-HAN CHANG, SHIH HUA HSIAO, BO CHENG HUANG, CHI YUAN CHEN, TING HSUAN CHUNG
  • Publication number: 20190168617
    Abstract: A method and a system for determining a discharging process of a battery are provided. The method includes the following steps. Measuring charging/discharging information of the battery. Calculating a charging/discharging characteristic of the battery according to the charging/discharging information. Aligning the charging/discharging characteristic of the battery according to a comparison characteristic point of a comparison characteristic to obtain an aligned charging/discharging characteristic. Determining whether the battery is normal according to the aligned charging/discharging characteristic or a coulombic efficiency of the battery. Calculating a safety probability of the battery according to the aligned charging/discharging characteristic and resistance of an internal short circuit of the battery when the battery is determined as abnormal. Determining a discharging process of the battery according to the safety probability of the battery.
    Type: Application
    Filed: December 28, 2017
    Publication date: June 6, 2019
    Inventors: Shou-Hung LING, Shih-Hao LIANG, Tzi-Cker CHIUEH, Deng-Tswen SHIEH, Mao-Cheng HUANG
  • Publication number: 20190172949
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Application
    Filed: January 18, 2019
    Publication date: June 6, 2019
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Publication number: 20190170802
    Abstract: A method and a system for detecting resistance of an internal short circuit of a battery are provided. The method includes the following steps. Measuring charging/discharging information of the battery. Calculating a charging/discharging characteristic of the battery according to the charging/discharging information. Aligning the charging/discharging characteristic of the battery according to a comparison characteristic point of a comparison characteristic to obtain an aligned charging/discharging characteristic. Determining whether the battery is normal according to the aligned charging/discharging characteristic or a coulombic efficiency of the battery; and when the battery is determined as abnormal, calculating aligned charging/discharging information according to the aligned charging/discharging characteristic, and calculating the resistance of the internal short circuit of the battery according to the aligned charging/discharging information.
    Type: Application
    Filed: June 7, 2018
    Publication date: June 6, 2019
    Inventors: Shou-Hung LING, Shih-Hao LIANG, Tzi-Cker CHIUEH, Deng-Tswen SHIEH, Mao-Cheng HUANG
  • Patent number: 10312925
    Abstract: This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 4, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Lung Chen, Ying-Cheng Wu, Shih-Hsiung Huang
  • Publication number: 20190165800
    Abstract: This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.
    Type: Application
    Filed: August 20, 2018
    Publication date: May 30, 2019
    Inventors: CHIH-LUNG CHEN, YING-CHENG WU, SHIH-HSIUNG HUANG
  • Patent number: 10164142
    Abstract: A flip chip light emitting diode includes a semiconductor layer comprising an epitaxial layer an N-semiconductor layer, a light active layer and a P-semiconductor layer arranged from top to bottom in series. A first electrode mounted on the semiconductor layer. A second electrode mounted on the semiconductor layer. A insulating layer mounted on the semiconductor layer. The N-semiconductor layer protrudes away from the epitaxial layer to form a protruding portion. The light active layer and the P-semiconductor layer mounts on the protruding portion in series. The insulating layer mounts between the first electrode and the protruding portion, the light active layer, the P-semiconductor layer and the second electrode. The flip chip light emitting diode also comprises a supporting portion, the supporting portion is mounted on a top surface of the epitaxial layer by a connecting portion. The connecting portion has same or different materials with the supporting portion.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 25, 2018
    Assignees: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC., Innolux Corporation
    Inventors: Po-Min Tu, Chien-Shiang Huang, Chien-Chung Peng, Tzu-Chien Hung, Shih-Cheng Huang, Chang-Ho Chen, Tsau-Hua Hsieh, Jong-Jan Lee, Paul-John Schuele
  • Patent number: 10109770
    Abstract: A light emitting diode includes a first electrode, a second electrode, and an epitaxial structure. The epitaxial structure is arranged on the first electrode, and electrically connects with the first electrode and the second electrode. The second electrode surrounds periphery of the epitaxial structure to reflect light from the epitaxial structure out from the top of the epitaxial structure. A method for manufacturing the light emitting diode is also presented. The light emitting diode and the method increase lighting efficiency of the light emitting diode.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 23, 2018
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC
    Inventors: Ching-Hsueh Chiu, Chia-Hung Huang, Ya-Wen Lin, Po-Min Tu, Shih-Cheng Huang
  • Patent number: 10050188
    Abstract: A light emitting diode chip comprises a light emitting diode chip core and a coating layer. The coating layer covers side surfaces of the light emitting diode chip core. And a display composed of the light emitting diode chips is also provided.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: August 14, 2018
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC
    Inventors: Chia-Hui Shen, Tzu-Chien Hung, Chien-Chung Peng, Chien-Shiang Huang, Shih-Cheng Huang, Chih-Jung Liu
  • Patent number: 10050176
    Abstract: An LED die includes a substrate, a pre-growth layer, a first insulating layer and a light emitting structure. The pre-growth layer, the first insulating layer and the light emitting structure are formed on the structure that order. The substrate includes a first electrode, a second electrode and an insulating part. The insulating part is formed between the first electrode and the second electrode. The LED die further includes a second insulating layer and a metal layer which are formed around the pre-growth layer. The present disclosure includes a method for manufacturing the LED die.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: August 14, 2018
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Ching-Hsueh Chiu, Ya-Wen Lin, Po-Min Tu, Shih-Cheng Huang
  • Publication number: 20180212105
    Abstract: A flip chip light emitting diode includes a semiconductor layer comprising an epitaxial layer an N-semiconductor layer, a light active layer and a P-semiconductor layer arranged from top to bottom in series. A first electrode mounted on the semiconductor layer. A second electrode mounted on the semiconductor layer. A insulating layer mounted on the semiconductor layer. The N-semiconductor layer protrudes away from the epitaxial layer to form a protruding portion. The light active layer and the P-semiconductor layer mounts on the protruding portion in series. The insulating layer mounts between the first electrode and the protruding portion, the light active layer, the P-semiconductor layer and the second electrode. The flip chip light emitting diode also comprises a supporting portion, the supporting portion is mounted on a top surface of the epitaxial layer by a connecting portion. The connecting portion has same or different materials with the supporting portion.
    Type: Application
    Filed: June 27, 2017
    Publication date: July 26, 2018
    Inventors: PO-MIN TU, CHIEN-SHIANG HUANG, CHIEN-CHUNG PENG, TZU-CHIEN HUNG, SHIH-CHENG HUANG, CHANG-HO CHEN, TSAU-HUA HSIEH, JONG-JAN LEE, PAUL-JOHN SCHUELE
  • Patent number: 9978728
    Abstract: A display apparatus and a fabricating method thereof are provided. The display apparatus includes a substrate, a light emitting diode, a first bump, a first insulating layer and a second insulating layer. The light emitting diode has a first surface and a second surface opposite each other, wherein the first surface faces the substrate. The light emitting diode is bonded to the substrate through the first bump. The first insulating layer is disposed on a periphery of the first bump and the light emitting diode, and contacts the first bump and the first surface. The second insulating layer is disposed on the substrate and surrounds at least a portion of the first insulating layer.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 22, 2018
    Assignees: Innolux Corporation, Advanced Optoelectronics Technology Inc.
    Inventors: Chun-Hsien Lin, Tsau-Hua Hsieh, Po-Min Tu, Tzu-Chien Hung, Chien-Chung Peng, Shih-Cheng Huang
  • Publication number: 20180040793
    Abstract: A light emitting diode chip comprises a light emitting diode chip core and a coating layer. The coating layer covers side surfaces of the light emitting diode chip core. And a display composed of the light emitting diode chips is also provided.
    Type: Application
    Filed: April 10, 2017
    Publication date: February 8, 2018
    Inventors: CHIA-HUI SHEN, TZU-CHIEN HUNG, CHIEN-CHUNG PENG, CHIEN-SHIANG HUANG, SHIH-CHENG HUANG, CHIH-JUNG LIU
  • Publication number: 20170373227
    Abstract: A light emitting diode includes a first electrode, a second electrode, and an epitaxial structure. The epitaxial structure is arranged on the first electrode, and electrically connects with the first electrode and the second electrode. The second electrode surrounds periphery of the epitaxial structure to reflect light from the epitaxial structure out from the top of the epitaxial structure. A method for manufacturing the light emitting diode is also presented. The light emitting diode and the method increase lighting efficiency of the light emitting diode.
    Type: Application
    Filed: August 22, 2017
    Publication date: December 28, 2017
    Inventors: CHING-HSUEH CHIU, CHIA-HUNG HUANG, YA-WEN LIN, PO-MIN TU, SHIH-CHENG HUANG
  • Publication number: 20170345801
    Abstract: A display apparatus and a fabricating method thereof are provided. The display apparatus includes a substrate, a light emitting diode, a first bump, a first insulating layer and a second insulating layer. The light emitting diode has a first surface and a second surface opposite each other, wherein the first surface faces the substrate. The light emitting diode is bonded to the substrate through the first bump. The first insulating layer is disposed on a periphery of the first bump and the light emitting diode, and contacts the first bump and the first surface. The second insulating layer is disposed on the substrate and surrounds at least a portion of the first insulating layer.
    Type: Application
    Filed: May 24, 2017
    Publication date: November 30, 2017
    Applicants: Innolux Corporation, Advanced Optoelectronic Technology Inc.
    Inventors: Chun-Hsien Lin, Tsau-Hua Hsieh, Po-Min Tu, Tzu-Chien Hung, Chien-Chung Peng, Shih-Cheng Huang