Patents by Inventor Shih-Cheng Huang

Shih-Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140175506
    Abstract: An LED epitaxial structure includes a substrate, a buffer layer and an epitaxial layer. The buffer layer is grown on a top surface of the substrate, and the epitaxial layer is formed on a surface of the buffer layer. The epitaxial layer has a first n-type epitaxial layer and a second n-type epitaxial layer. The first n-type epitaxial layer is formed between the buffer layer and the second n-type epitaxial layer. The first n-type epitaxial layer has a plurality of irregular holes therein. The first n-type epitaxial layer has a doping concentration which varies along a thickness direction of the first n-type epitaxial layer.
    Type: Application
    Filed: February 26, 2014
    Publication date: June 26, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: PO-MIN TU, SHIH-CHENG HUANG
  • Patent number: 8754438
    Abstract: An LED comprises a substrate, a buffer layer, an epitaxial layer and a conductive layer. The epitaxial layer comprises a first N-type epitaxial layer, a second N-type epitaxial layer, and a blocking layer with patterned grooves sandwiched between the first and second N-type epitaxial layers. The first and second N-type epitaxial layers make contact each other via the patterned grooves. Therefore, the LED enjoys a uniform current distribution and a larger light emitting area. A manufacturing method for the LED is also provided.
    Type: Grant
    Filed: February 19, 2012
    Date of Patent: June 17, 2014
    Assignee: Advanced Optoelectronics Technology, Inc.
    Inventors: Ya-Wen Lin, Shih-Cheng Huang, Po-Min Tu, Chia-Hung Huang, Shun-Kuei Yang
  • Patent number: 8748913
    Abstract: An LED module includes a base, a circuit layer formed on the base and multiple LEDs each having an LED die connecting to the circuit layer. The circuit layer includes multiple connecting sections. Each connecting section includes a first connecting part and a second connecting part electrically insulating and spaced from each other. Each LED includes an electrode layer having a first section and a second section electrically insulated from the first section and respectively electrically connecting the first and second connecting parts of a corresponding connecting section. The LED die is electrically connected to the second section. A transparent electrically conductive layer is formed on the LED die and electrically connects the LED die to the first section of the electrode layer. An electrically insulating layer is located between the LED die and surrounding the LED die except where the transparent electrically conductive layer connects.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: June 10, 2014
    Assignee: Advanced Optoelectronics Technology, Inc.
    Inventors: Shih-Cheng Huang, Po-Min Tu
  • Patent number: 8742443
    Abstract: An LED epitaxial structure includes a substrate, a buffer layer, a functional layer and a light generating layer. The buffer layer is located on a top surface of the substrate. The functional layer includes a plurality of high-temperature epitaxial layers and low-temperature epitaxial layers alternatively arranged between the buffer layer and light generating layer. A textured structure is formed in the low-temperature epitaxial layer. A SiO2 layer including a plurality of convexes is located on the textured structure to increase light extraction efficiency of the LED epitaxial structure. A manufacturing method of the LED epitaxial structure is also disclosed.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: June 3, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Ya-Wen Lin, Shih-Cheng Huang, Po-Min Tu
  • Patent number: 8735919
    Abstract: A group III-nitride based semiconductor LED includes a sapphire substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer grown sequentially on the sapphire substrate. An n-type strain lattice structure is arranged between the n-type semiconductor layer and the active layer. A lattice constant of the n-type strain lattice structure exceeds that of the active layer, and is less than that of the n-type semiconductor layer.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: May 27, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang
  • Publication number: 20140141553
    Abstract: A method for manufacturing a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer totally covering the protrusions; forming a plurality of semiconductor islands on an upper surface of the un-doped GaN layer by self-organized growth, gaps being formed between two adjacent semiconductor islands to expose a part of the upper surface of the un-doped GaN layer; forming an n-type GaN layer on the exposed part of the upper surface of the un-doped GaN layer, the n-type GaN layer being laterally grown to totally cover the semiconductor islands; forming an active layer on an upper surface of the n-type GaN layer; and forming a p-type GaN layer on the active layer.
    Type: Application
    Filed: September 25, 2013
    Publication date: May 22, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: CHING-HSUEH CHIU, YA-WEN LIN, PO-MIN TU, SHIH-CHENG HUANG
  • Publication number: 20140134774
    Abstract: A method for making a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer partly covering the protrusions to expose a part of each of the protrusions; etching the un-doped GaN layer to expose a top end of each of the protrusions; and forming an n-type GaN layer, an active layer, and a p-type GaN layer sequentially on the top ends of the protrusions and the un-doped GaN layer.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 15, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: CHING-HSUEH CHIU, YA-WEN LIN, PO-MIN TU, SHIH-CHENG HUANG
  • Publication number: 20140131727
    Abstract: A method for manufacturing a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer having an upper part covering top ends of the protrusions; forming a distributed bragg reflective layer on the un-doped GaN layer until the distributed bragg reflective layer totally covering the protrusions and the un-doped GaN layer; etching the distributed bragg reflective layer and the upper part of the un-doped GaN layer to expose the top ends of the protrusions; and forming an n-type GaN layer, an active layer, and a p-type GaN layer sequentially on the top ends of the protrusions and the distributed bragg reflective layer. An LED chip formed by the method described above is also provided.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 15, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: CHING-HSUEH CHIU, YA-WEN LIN, PO-MIN TU, SHIH-CHENG HUANG
  • Publication number: 20140131656
    Abstract: A light emitting diode chip includes a sapphire substrate and a plurality of carbon nano-tubes arranged on an upper surface of the sapphire substrate. Gaps are formed between two adjacent carbon nano-tubes to expose parts of the upper surface of the sapphire substrate. An un-doped GaN layer is formed on the exposed parts of the upper surface of the sapphire substrate and covers the carbon nano-tubes. An n-type GaN layer, an active layer and a p-type GaN layer are formed on the un-doped GaN layer in sequence. A method for manufacturing the light emitting diode chip is also provided.
    Type: Application
    Filed: August 30, 2013
    Publication date: May 15, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: YA-WEN LIN, CHING-HSUEH CHIU, PO-MIN TU, SHIH-CHENG HUANG
  • Publication number: 20140106485
    Abstract: An LED manufacturing method includes following steps: providing an LED die; providing an electrode layer having a first section and a second section electrically insulated from the first section, and arranging the LED die on the second section wherein an electrically conductive material electrical connects a bottom of the LED die with second section; forming a transparent conductive layer to electrically connect a top of the LED die with the first section; providing a base and coating an outer surface of the base with a layer of electrically conductive material, defining a continuous gap in the electrically conductive material to divide the electrically conductive material into a first electrode part, and a second electrode part, arranging the electrode layer on the base so that the first section contacts the first electrode part, and the second section contacts the second electrode part.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Po-Min TU, Shih-Cheng HUANG, Ya-Wen LIN
  • Patent number: 8697465
    Abstract: An LED epitaxial structure includes a substrate, a buffer layer and an epitaxial layer. The buffer layer is grown on a top surface of the substrate, and the epitaxial layer is formed on a surface of the buffer layer. The epitaxial layer has a first n-type epitaxial layer and a second n-type epitaxial layer. The first n-type epitaxial layer is formed between the buffer layer and the second n-type epitaxial layer. The first n-type epitaxial layer has a plurality of irregular holes therein.
    Type: Grant
    Filed: November 20, 2011
    Date of Patent: April 15, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang
  • Publication number: 20140073077
    Abstract: A method for epitaxial growth of a light emitting diode, includes following steps: providing a substrate; forming a buffer layer on the substrate; forming a first epitaxial layer on the buffer layer in a first temperature; forming a second epitaxial layer on the first epitaxial layer in a second temperature lower than the first temperature, thereby forming a first rough surface on the second epitaxial layer; etching the second epitaxial layer and the first epitaxial layer until a second rough surface is formed on the first epitaxial layer; forming a mask layer on the rough surface of the first epitaxial layer; partly etching the mask layer to form a plurality of protrusions with the first epitaxial layer exposed thereamong; and forming an N-type epitaxial layer, an active layer and a P-type epitaxial layer on the first epitaxial layer in sequence.
    Type: Application
    Filed: August 5, 2013
    Publication date: March 13, 2014
    Applicant: Advanced Optoelectronic Technology, Inc.
    Inventors: YA-WEN LIN, SHIH-CHENG HUANG, PO-MIN TU
  • Publication number: 20140065743
    Abstract: An exemplary method of manufacturing a light emitting diode (LED) die includes steps: providing a preformed LED structure, the LED structure including a first substrate, and a nucleation layer, a buffer layer, an N-type layer, a muti-quantum well layer and an P-type layer formed successively on the first substrate; forming at least one insulation block on the P-type layer; forming a mirror layer on the on the P-type layer and covering the insulation block; forming a conductive second substrate on the mirror layer; removing the first substrate, the nucleation layer and the buffer layer and exposing a bottom surface of the N-type layer; and disposing one N-electrode on the exposed surface of the N-type layer. The N-electrode is located corresponding to the insulation block.
    Type: Application
    Filed: August 14, 2013
    Publication date: March 6, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: YA-WEN LIN, SHIH-CHENG HUANG, PO-MIN TU
  • Publication number: 20140065745
    Abstract: A manufacturing method for an LED (light emitting diode) includes following steps: providing a substrate; disposing a transitional layer on the substrate, the transitional layer comprising a planar area with a flat top surface and a patterned area with a rugged top surface; coating an aluminum layer on the transitional layer; using a nitriding process on the aluminum layer to form an AlN material on the transitional layer; disposing an epitaxial layer on the transitional layer and covering the AlN material, the epitaxial layer contacting the planar area and the patterned area of the transitional layer, a plurality of gaps being defined between the epitaxial layer and the slugs of the second part of the AlN material in the patterned area of the transitional layer.
    Type: Application
    Filed: November 5, 2013
    Publication date: March 6, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: CHIA-HUNG HUANG, SHIH-CHENG HUANG, PO-MIN TU, YA-WEN LIN, SHUN-KUEI YANG
  • Patent number: 8664026
    Abstract: A method for fabricating a semiconductor lighting chip includes steps of providing a substrate with an epitaxial layer thereon. The epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer successively grown on the substrate. The epitaxial layer has dislocation defects traversing the first semiconductor layer, the active layer and the second semiconductor layer. The epitaxial layer is then subjected to an etching process which remove parts of the second semiconductor layer and the active layer along the dislocation defects to form recesses recessing from the second semiconductor layer to the active layer. Thereafter a first electrode and a second electrode are formed on the first semiconductor layer and the second semiconductor layer, respectively.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: March 4, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang
  • Patent number: 8643022
    Abstract: An LED comprises an electrode layer comprising a first a second sections electrically insulated from each other; an electrically conductive layer on the second section, an electrically conductive pole protruding from the electrically conductive layer; an LED die comprising an electrically insulating substrate on the electrically conductive layer, and a P-N junction on the electrically insulating substrate, the P-N junction comprising a first electrode and a second electrode, the electrically conductive pole extending through the electrically insulating substrate to electrically connect the first electrode to the second section; a transparent electrically conducting layer on the LED die, the transparent electrically conducting layer electrically connecting the second electrode to the first section; and an electrically insulating layer between the LED die, the electrically conductive layer, and the transparent electrically conducting layer, wherein the electrically insulating layer insulates the transparent ele
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 4, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang, Ya-Wen Lin
  • Publication number: 20140027806
    Abstract: A semiconductor optoelectronic structure with increased light extraction efficiency, includes a substrate; a buffer layer is formed on the substrate and includes a pattern having plural grooves formed adjacent to the substrate; a semiconductor layer is formed on the buffer layer and includes an n-type conductive layer formed on the buffer layer, an active layer formed on the n-type conductive layer, and a p-type conductive layer formed on the active layer; a transparent electrically conductive layer is formed on the semiconductor layer; a p-type electrode is formed on the transparent electrically conductive layer; and an n-type electrode is formed on the n-type conductive layer.
    Type: Application
    Filed: September 26, 2013
    Publication date: January 30, 2014
    Inventors: SHIH-CHENG HUANG, PO-MIN TU, PENG-YI WU, WEN-YU LIN, CHIH-PANG MA, TZU-CHIEN HUNG, CHIA-HUI SHEN
  • Publication number: 20140021486
    Abstract: A light emitting diode (LED) includes a substrate and an eputaxial layer on the substrate. The epitaxial layer includes a N-type GaN-based layer, a light emitting layer, and a P-type GaN-based layer. The LED further includes a first electrode on the N-type GaN-based layer and a second electrode on the P-type GaN-based layer. The P-type GaN-based layer has a inactive portion, and the second electrode is located and covers the inactive portion.
    Type: Application
    Filed: June 3, 2013
    Publication date: January 23, 2014
    Inventors: YA-WEN LIN, SHIH-CHENG HUANG, PO-MIN TU
  • Publication number: 20140014899
    Abstract: A multi-quantum well structure includes two first barrier layers, two well layers sandwiched between the two first barrier layers, and a doped second barrier layer sandwiched between the two well layers. The second barrier layer has its conduction band and forbidden band gradually transiting to those of one of the well layers, and a dopant concentration of the second barrier layer gradually changes along a direction from one well layer to the other. The invention also relates to a light emitting diode structure having the multi-quantum well structure.
    Type: Application
    Filed: July 4, 2013
    Publication date: January 16, 2014
    Inventors: SHIH-CHENG HUANG, YA-WEN LIN, PO-MIN TU
  • Patent number: 8629534
    Abstract: A semiconductor structure includes a Si substrate, a supporting layer and a blocking layer formed on the substrate and an epitaxy layer formed on the supporting layer. The supporting layer defines a plurality of grooves therein to receive the blocking layer. The epitaxy layer is grown from the supporting layer. A plurality of slots is defined in the epitaxy layer and over the blocking layer. The epitaxy layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 14, 2014
    Assignee: Advanced Optoelectronics Technology, Inc.
    Inventors: Shih-Cheng Huang, Po-Min Tu, Shun-Kuei Yang, Chia-Hung Huang