Patents by Inventor Shih-Chi Chen

Shih-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200105533
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
  • Publication number: 20200106155
    Abstract: A back cover includes a metal body having a first side, a second side, and a groove that is formed at the first side. The metal body further has a first radiator, a second radiator, and a ground radiator. The first radiator is disposed in the groove, and has a main portion and a support portion that cooperatively form a T-shape. The main portion includes a feeding end adjacent to a closed end of the groove. The second radiator is adjacently connected to the groove and is defined by the first and second sides, and an edge of the groove. The ground radiator is formed by a portion of the metal body excluding the first and second radiators. The second radiator and the support portion are connected to the ground radiator. The first and second radiators, and the ground radiator are serve as an antenna structure.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 2, 2020
    Applicant: Acer Incorporated
    Inventors: Shih-Ting Huang, Ching-Chi Lin, Chien-Wen Chen, Chuan-Chun Wang
  • Patent number: 10603688
    Abstract: The present application discloses a microtome. The microtome includes: a blade cutting a soft material in a first direction, the first direction being a feeding direction of the soft material; a blade holder holding the blade; an actuator providing a vibration in a second direction along a cutting edge of the blade; and a frequency-tunable resonator driven by the actuator into vibration and fixedly connected to the blade holder to transfer the vibration to the blade holder and the blade, the resonator having a tunable resonant frequency in the second direction.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: March 31, 2020
    Assignee: The Chinese University of Hong Kong
    Inventors: Shih-Chi Chen, Ji Wang, Chenglin Li
  • Publication number: 20200098640
    Abstract: The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.
    Type: Application
    Filed: April 5, 2019
    Publication date: March 26, 2020
    Applicant: Taiwan Semiconductorr Manufacturing Co., Ltd.
    Inventors: Chandrashekhar Prakash SAVANT, Chia-Ming Tsai, Ming-Te Chen, Shih-Chi Lin, Zack Chong, Tien-Wei Yu
  • Patent number: 10591646
    Abstract: An infrared anti-reflection film structure, an anti-reflection film layer, including a material of zinc oxide, comprising a top anti-reflection film layer and a bottom anti-reflection film layer, wherein the top anti-reflection film layer is disposed on a top side of the base material and the bottom anti-reflection film layer is disposed on a bottom side of the base material; and the base material is manufactured by a floating zone crystal growth method. Through the silicon base material manufactured by the high purity crystal growth method, the silicon base material replaces germanium as the high refractive index material and base material. And coating the anti-reflection film layer on the surface of the silicon base material, so as to apply the infrared anti-reflection film structure to the thermal imaging technology.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 17, 2020
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Shih-Hao Chan, Shiang-Feng Tang, Shao-Ze Tseng, Kun-Chi Lo, Sheng-Hui Chen, Wen-Jen Lin
  • Publication number: 20200083390
    Abstract: An image sensor with an absorption enhancement semiconductor layer is provided. In some embodiments, the image sensor comprises a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked. The absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers. The absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer. Further, the image sensor comprises a plurality of protrusions and a photodetector. The protrusions are defined by the back-side semiconductor layer, and the photodetector is defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Ming-Chi Wu, Chien Nan Tu, Kun-Yu Lin, Shih-Shiung Chen
  • Publication number: 20200083389
    Abstract: An image sensor with an absorption enhancement semiconductor layer is provided. In some embodiments, the image sensor comprises a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked. The absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers. The absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer. Further, the image sensor comprises a plurality of protrusions and a photodetector. The protrusions are defined by the back-side semiconductor layer, and the photodetector is defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Ming-Chi Wu, Chien Nan Tu, Kun-Yu Lin, Shih-Shiung Chen
  • Patent number: 10586902
    Abstract: A light-emitting device includes a light-emitting structure with a side surface, and a reflective layer covering the side surface. The light-emitting structure has a first light-emitting angle and a second light-emitting angle. The difference between the first light-emitting angle and the second light-emitting angle is larger than 15°.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 10, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Liang Liu, Ming-Chi Hsu, Shih-An Liao, Chun-Hung Liu, Zhi-Ting Ye, Cheng-Teng Ye, Po-Chang Chen, Sheng-Che Chiou
  • Publication number: 20200058608
    Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Kuo-Yu Cheng, Chih-Ping Chao, Kuan-Chi Tsai, Shih-Shiung Chen, Wei-Kung Tsai
  • Publication number: 20200020625
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Publication number: 20200006410
    Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.
    Type: Application
    Filed: September 4, 2018
    Publication date: January 2, 2020
    Inventors: Ming-Chi Wu, Chun-Chieh Fang, Bo-Chang Su, Chien Nan Tu, Yu-Lung Yeh, Kun-Yu Lin, Shih-Shiung Chen
  • Patent number: 10522585
    Abstract: A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other. The conductive layer is disposed on the first surface of the substrate. The transparent layer is disposed on the conductive layer. The transparent hard mask layer is disposed on the transparent layer, in which the substrate has an etch selectivity with respect to the transparent hard mask layer. The device layer is disposed between the carrier and the second surface of the substrate, in which various portions of the device layer are respectively exposed by various through holes which pass through the transparent hard mask layer, the transparent layer, the conductive layer, and the substrate.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Fang Yang, Yi-Hung Chen, Keng-Ying Liao, Yi-Jie Chen, Shih-Hsun Hsu, Chun-Chi Lee
  • Publication number: 20190385929
    Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
    Type: Application
    Filed: March 1, 2019
    Publication date: December 19, 2019
    Inventors: Shih-Chang Ku, Hung-Chi Li, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Patent number: 10510910
    Abstract: An image sensor with an absorption enhancement semiconductor layer is provided. In some embodiments, the image sensor comprises a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked. The absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers. The absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer. Further, the image sensor comprises a plurality of protrusions and a photodetector. The protrusions are defined by the back-side semiconductor layer, and the photodetector is defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chi Wu, Chien Nan Tu, Kun-Yu Lin, Shih-Shiung Chen
  • Patent number: 10497571
    Abstract: A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Publication number: 20190353912
    Abstract: An apparatus and a method for laser beam shaping and scanning. The apparatus includes a digital micromirror device (DMD) including a plurality of micromirrors, configured to receive a first laser beam, adjust an axial position of a focal point of the first laser beam along a moving direction of the first laser beam by controlling a focal length of wavefront of a binary hologram applied to the DMD, and adjust a lateral position of the focal point on a plane perpendicular to the moving direction by controlling a tilted angle of a fringe pattern and a period of fringes of the binary hologram applied to the DMD, wherein the DMD simultaneously functions as programmable binary mask and a blazed grating.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 21, 2019
    Inventors: Shih-Chi CHEN, Qiang GENG, Dien WANG, Pengfei CHEN, Dapeng ZHANG
  • Publication number: 20190353913
    Abstract: A laser-based manufacturing system is disclosed for fabricating non-planar three-dimensional layers. The system may have a laser for producing a laser beam with a plurality of optical wavelengths. An optically dispersive element may be used for receiving the laser beam and splitting the beam into a plurality of distinct beam components, wherein each beam component has spatially separated optical spectral components. A phase mask may be used which is configured to receive at least one of the beam components emerging from the dispersive element and to create a modified beam. One or more focusing elements may then be used to receive the modified beam emerging from the phase mask and to focus the modified beam into a non-planar light sheet for use in fabricating a part.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 21, 2019
    Inventors: Sourabh SAHA, Shih-Chi CHEN, Yina CHANG
  • Patent number: 10468349
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Publication number: 20190333769
    Abstract: A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.
    Type: Application
    Filed: April 27, 2018
    Publication date: October 31, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
  • Patent number: 10460241
    Abstract: A server and a cloud computing resource optimization method thereof for big data cloud computing architecture are provided. The server runs a dynamic scaling system to perform the following operations: receiving a task message; executing a profiling procedure to generate a profile based on an to-be-executed task recorded in the task message; executing a classifying procedure to determine a task classification of the to-be-executed task; executing a prediction procedure to obtain a plurality of predicted execution times corresponding to a plurality of computing node numbers, a computing node type and a system parameter of the to-be-executed task; executing an optimization procedure to determine a practical computing node number of the to-be-executed task; and transmitting an optimization output message to a management server to make the management server allocate at least one data computing system to execute a program file of the to-be-executed task.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: October 29, 2019
    Assignee: Institute For Information Industry
    Inventors: Jerry Chi-Yuan Chou, Shih-Yu Lu, Chen-Chun Chen, Chan-Yi Lin, Hsin-Tse Lu