Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.

Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A one-time programmable memory structure comprises: A transistor includes a gate. A capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is disposed on the first electrode. A top surface of the first electrode and a top surface of the gate are located on a same plane perpendicular to a direction of the first electrode toward the second electrode. An interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode. A resistor comprises a conductive layer. Top and bottom surfaces of the conductive layer are respectively located on a same plane, perpendicular to the direction of the first electrode toward the second electrode, with the top and bottom surfaces of the gate.

Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.

Abstract: A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

Abstract: A computing system initialization system includes a BIOS processing system coupled to a computing device via a first I/O access connection, to a BIOS memory system via a second I/O access connection that is a relatively higher speed I/O access connection than the first I/O connection, and to a BIOS module. The BIOS processing system retrieves device data from the computing device via the first I/O access connection, stores the device data in the BIOS memory system via the second I/O access connection, and performs initialization operations subsequent to storing the device data in the BIOS memory system. During the initialization operations, the BIOS processing determines that the BIOS module requires the device data and, in response, retrieves the device data from the BIOS memory system via the second I/O access connection, and provides the device data that was retrieved from the BIOS memory system to the BIOS module.

Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

Abstract: A computing system initialization system includes a computing device that is coupled to a management device and that includes a processing system having at least one register storing debug-message-display-determination instructions, and a memory system that is coupled to the processing system and that includes Basic Input/Output System (BIOS) instructions that, when executed by the processing system, cause the processing system to provide a BIOS engine. The BIOS engine begins initialization operations and, during those initialization operations, generates at least one first debug message. The BIOS engine then accesses the at least one register included in the processing system to execute the debug-message-display-determination instructions and, in response, determines that the at least one first debug message should be displayed. In response, the BIOS engine transmits the at least one first debug message to the management device such that the management device displays the at least one first debug message.

Abstract: A computing system initialization system includes a computing device that is coupled to a management device and that includes a processing system having at least one register storing debug-message-display-determination instructions, and a memory system that is coupled to the processing system and that includes Basic Input/Output System (BIOS) instructions that, when executed by the processing system, cause the processing system to provide a BIOS engine. The BIOS engine begins initialization operations and, during those initialization operations, generates at least one first debug message. The BIOS engine then accesses the at least one register included in the processing system to execute the debug-message-display-determination instructions and, in response, determines that the at least one first debug message should be displayed. In response, the BIOS engine transmits the at least one first debug message to the management device such that the management device displays the at least one first debug message.

Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.

Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

Abstract: A wireless sound output device includes a wireless earbud and a charging base. The wireless earbud is placed in the charging base. If a true wireless stereo Bluetooth controller of the wireless earbud detects that a mode switching circuit of the charging base is switched to a wireless Bluetooth receiver mode, an analog signal is transmitted to an audio source output hole of the charging base through an audio source analog signal output switching unit of the wireless earbud.

Abstract: A detection substrate includes a substrate, a wetting layer, a barrier layer, a reaction layer, a counter electrode layer, a reference electrode layer, an insulating frame, and a plurality of wirings. The substrate includes a counter electrode, a working electrode, and a reference electrode. The reaction layer is located on the barrier layer. A surface of the reaction layer has a naturally micro-etched nano pattern. The counter electrode layer has an accommodating area which accommodates the reaction layer, and the naturally micro-etched nano pattern is exposed from the accommodating area. The insulating frame is located on a measurement area. The detection substrate has electrodes. During use, a predetermined reaction potential is applied to the detection substrate by an electrochemical device, and a Raman spectroscopy analysis is performed to obtain a strengthened Raman spectroscopy signal. A Raman spectrum detection system and a Raman spectrum detection method are also provided.

Abstract: A cloud data sharing method supporting native applications and containerized applications, including: using a user-space file system to mount at least one cloud storage server to a virtual file system; using a cloud agent module to register a push notification service with a cloud storage service module of each cloud storage server, so that when the content of a file stored in one cloud storage server is altered, the cloud agent module can receive a content-altered notification of the file and send the content-altered notification to a message broker module; and using the message broker module to accept a file-altered-notification subscription from at least one native application or at least one containerized application, so that when the message broker module receives the file-altered notification from the cloud agent module, the message broker module can publish a file-altered message to one native application or one containerized application.

Abstract: A wireless sound output device includes a wireless earbud and a charging base. The wireless earbud is placed in the charging base. If a true wireless stereo Bluetooth controller of the wireless earbud detects that a mode switching circuit of the charging base is switched to a wireless Bluetooth receiver mode, an analog signal is transmitted to an audio source output hole of the charging base through an audio source analog signal output switching unit of the wireless earbud.

Abstract: An externally-connected shop floor control (SFC) system comprising M shop floor control (SFC) devices is disclosed. By letting each of the M SFC devices be electrically connected between one test machine and one information read-out device, the SFC system is successfully implemented into a production line. Therefore, each of the M SFC devices is adopted to achieve a re-verification of pass record for a test object that is transferred from a previous-stage test machine, and is also adopted for collecting related test data of the test object transferred from a current-stage test machine. As such, the SFC system can be easily implemented into any one type of production line, so as to assist the manager of the production line in data collection, station passing control, manufacturing reports, and control of production efficiency and yield, without spending much cost of human resources and software/firmware developing.

Abstract: A computing system initialization system includes a computing device that is coupled to a management device and that includes a processing system having at least one register storing debug-message-display-determination instructions, and a memory system that is coupled to the processing system and that includes Basic Input/Output System (BIOS) instructions that, when executed by the processing system, cause the processing system to provide a BIOS engine. The BIOS engine begins initialization operations and, during those initialization operations, generates at least one first debug message. The BIOS engine then accesses the at least one register included in the processing system to execute the debug-message-display-determination instructions and, in response, determines that the at least one first debug message should be displayed. In response, the BIOS engine transmits the at least one first debug message to the management device such that the management device displays the at least one first debug message.