Abstract: A method for communicating with an under-test object and a communicating system are provided. The method includes the following steps. A command signal is provided from a processing unit of the communicating system to the under-test object, and the processing unit waits for receiving a response signal from the under-test object. If the response signal from the under-test object 5 has not been received by the processing unit for a predetermined waiting time period, the command signal is provided to the under-test object again and the predetermined waiting time period is adjusted. There is an exponential relation between the predetermined waiting time period and the number of times the command signal is provided to the under-test object.

Abstract: A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

Abstract: A JBOD apparatus (1) having a hard disk drive (HDD) expander (11), a switch (13) and a BMC module (12) is disclosed. The HDD expander (11) is connected to a plurality of hard drives (5) respectively. The switch (13) connects the HDD expander (11) with a connecting port (14) for enabling a first transmission channel, or connects the HDD expander (11) with the BMC module (12) for enabling a second transmission channel. The BMC module (12) is connected to an Ethernet through a network port (17). The HDD expander (11) initially receives a wired transmitted command through the first transmission channel. When the BMC module (12) receives an Ethernet transmitted command through the Ethernet, it controls the switch (13) to change for enabling the second transmission channel, therefore, the BMC module (12) executes an interactive operation with the HDD expander (11) in accordance with the Ethernet transmitted command.

Abstract: A control module of a node comprising a baseboard management controller (BMC), a first memory and a second memory is present. The first memory stores a working firmware, the second memory stores a default firmware. The BMC normally connects with the first memory and reads the working firmware to boot during a booting procedure. If the BMC cannot boot through executing the working firmware after a firmware updating procedure executed for updating the working firmware failed, it switches to connect with the second memory and reads the default firmware to replace with the working firmware to boot. After the BMC boots through the default firmware successfully, it switches back to connect with the first memory, and re-updates the working firmware again.

Abstract: A rack having a plurality of fans and a plurality of servers divided into several groups is presented. Each of the servers calculates fan speed needed for heat dissipating based on internal temperatures, and outputs the calculated fan speed to the fans in same group respectively. The fans in the same group run according to the received fan speed. A rack management controller (RMC) in the rack obtains the fan speed outputted by a server in one of the several groups, and calculates a fan speed compensating value based on the obtained fan speed. The RMC then outputs the fan speed compensating value to fans in neighboring groups to make it to run according to the fan speed compensating value.

Abstract: A rack comprising a control module and a plurality of nodes is present. The control module comprises a rack management controller (RMC), and each of the plurality of nodes comprises a baseboard management controller (BMC). The RMC communicates with the BMCs respectively through a plurality of default communication channels, and the RMC controls the nodes and transmits necessary data thereto through the BMCs. When losing response signal from one of the BMCs, the RMC resends same signal to the non-responded BMC. If a resend threshold is achieved, the RMC sends a control signal to a reset pin of the non-responded BMC directly through a GPIO channel to force the non-responded BMC to reset.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.

Abstract: A rack having multiple rack management modules is disclosed. Each rack management module respectively comprises a Rack Management Controller (RMC), a switch and a memory, wherein the switch of each rack management module is interconnected, a firmware is saved on each memory respectively. When the RMC receives a firmware update image and an updating command uploaded externally, the RMC sends a switching instruction to the switch for enabling the switch to switch and connect to the memory of another rack management module. When the RMC executes a firmware updating procedure, the firmware in the memory of another rack management module is updated via switch connection. The present invention can effectively avoid the issue that the RMC is not able to boot normally after the firmware updating fails leading to that the rack is not able to re-update the firmware.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; depositing a liner on the gate structure and the substrate; and performing an etching process by injecting a gas comprising CH3F, O2, and He for forming a spacer adjacent to the gate structure.

Abstract: The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler.

Abstract: A method for manufacturing a panel display is provided. The panel display includes a frame, an elastic pad, and a display panel. The frame has a supporting tray and a side wall which perpendicularly extends from the end of the supporting tray. A groove is formed on the supporting tray adjacent to the foot of the side wall. One end of the elastic pad is located within the groove while the other end leans on the side wall before the display panel is configured with the frame. When entering the display panel into the frame, the edge of the display panel compels the elastic pad to bend and form a bottom portion and a side portion. The bottom portion is accommodated in the groove while the side portion is compressed by the edge of the display panel and lies on the side wall.

Abstract: A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

Abstract: A test key structure for use in measuring step height includes a substrate, and a pair of test contacts. The substrate includes an isolation region and a diffusion region. The test contact pair includes a first test contact and a second test contact for measuring electrical resistances. The first test contact is disposed on the diffusion region and the second test contact is disposed on the isolation region.

Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.

Abstract: A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.

Abstract: A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.

Abstract: A capacitive sensing array device of an electronic apparatus includes sensing electrodes, a shielding conductor layer, a coupling signal source, a constant voltage source and switch modules. The coupling signal source provides a coupling signal coupled to an object. The constant voltage source provides a constant voltage to the shielding conductor layer to form a stable vertical parasitic capacitor between the shielding conductor layer and each sensing electrode. Each switch module is electrically connected to the constant voltage source via the corresponding sensing electrode. When one sensing electrode is selected to perform sensing, the corresponding switch module is configured as an open-circuited state such that the selected sensing electrode is disconnected from the constant voltage source, while the other sensing electrodes are electrically connected to the constant voltage source to form a stable horizontal parasitic capacitor between the selected sensing electrode and the other sensing electrodes.