Abstract: A method of protecting a shallow trench isolation structure is described, which is applied to a semiconductor device process that includes a first process causing a recess in the STI structure and a second process after the first process. The method includes forming a silicon nitride layer in the recess along the profile of the same during the second process.

Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

Abstract: A method of processing nature pattern on expitaxial substrate, unlike the conventional method of processing regular pattern on expitaxial substrate (such as sapphire substrate) by lithography, wet etches a sapphire substrate directly to obtain a nature pattern, so as to simplify the fabrication process. Compared with the conventional way of processing pattern sapphire, the nature pattern sapphire substrate produced by the method can avoid voids between the interface of sapphire and GaN and apply this technology to a wired bond LED structure to increase the sidewall light extraction and improve the texture of the sapphire surface of a flip chip LED structure. In addition, this method also can be applied to a thin-GaN LED for achieving the surface texture after the sapphire is removed by laser.

Abstract: A method for manufacturing a metal-oxide semiconductor (MOS) transistor includes providing a substrate having at least a gate structure and a shallow trench isolation (STI) formed thereon, performing a first etching process to form recesses in the substrate respectively at two sides of the gate structure, performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in the recesses respectively, accordingly a seam is formed in between the epitaxial silicon layer and the STI, forming a dielectric layer in the seam, and performing a self-aligned silicide (salicide) process.

Abstract: A method for fabricating a light emitting diode (LED) is provided. A first-type doped semiconductor layer, a light emitting layer and a second-type doped semiconductor layer are formed on an epitaxy substrate sequentially. Then, a gold layer is formed on the second-type doped semiconductor layer. Next, a bonding substrate is provided. The bonding substrate includes a silicon substrate and a germanium-contained layer disposed on the silicon substrate. Then, a bonding process is performed on the bonding substrate and the gold layer. Next, the epitaxy substrate is removed. Accordingly, a LED with better reliability and light-emitting efficiency can be made. Moreover, a LED is also provided.

Abstract: A method for fabricating a light emitting diode (LED) is provided. First, a first type doped semiconductor layer, an emitting layer and a second type doped semiconductor layer are sequentially formed on an epitaxy substrate. Then, a gold layer is formed on the second type doped semiconductor layer. Next, a silicon substrate is provided, and a wafer bonding process is performed between the silicon substrate and the gold layer. Finally, the epitaxy substrate is removed. As mentioned above, a LED with better reliability and efficiency of light-emitting is fabricated according to the method provided by the present invention. Moreover, the present invention further provides a LED.

Abstract: A method for fabricating a light emitting diode (LED) is provided. First, a first type doped semiconductor layer, an emitting layer and a second type doped semiconductor layer are sequentially formed on an epitaxy substrate. Then, a first transparent conductive layer is formed on the second type doped semiconductor layer. Next, a substitution substrate having a second transparent conductive layer formed thereon is provided. Then, a wafer bonding process is performed on the epitaxy substrate and the substitution substrate, so as to bond the first transparent conductive layer and the second transparent conductive layer. Finally, the epitaxy substrate is removed. As mentioned above, an LED with better reliability is fabricated according to the method provided by the present invention. Moreover, the present invention further provides an LED.

Abstract: A method for fabricating a light emitting diode (LED) is provided. A first-type doped semiconductor layer, a light emitting layer and a second-type doped semiconductor layer are formed on an epitaxy substrate sequentially. Then, a gold layer is formed on the second-type doped semiconductor layer. Next, a bonding substrate is provided. The bonding substrate includes a silicon substrate and a germanium-contained layer disposed on the silicon substrate. Then, a bonding process is performed on the bonding substrate and the gold layer. Next, the epitaxy substrate is removed. Accordingly, a LED with better reliability and light-emitting efficiency can be made. Moreover, a LED is also provided.

Abstract: A solder composition adapted to bond metallic materials and non-metallic materials is provided. The solder composition can enhance the bonding strength for the metallic materials and the non-metallic materials. The solder composition mainly comprises Sn—Cr alloy. The solder composition further includes anther metal component for regulating the bonding capability so that the solder composition can be used to bond various materials.

Abstract: A system and method for editing a bitstream is provided. A first segment is cut from a first bitstream and a second segment is cut from a second bitstream. In cutting the segments from the bitstreams, first and last GOPs in the segments can be cut between frames in the GOP. The number of frames of the broken GOP is then compared to a pre-determined threshold value. If the number of frames of the broken GOP is less than or equal to the threshold value, the broken GOP is combined with a neighboring GOP. Therefore, the newly created GOP is longer than the standard size regular GOP. However, if the number of frames in the broken GOP is greater than the threshold value, a new GOP is created with the frames of the broken GOP. Therefore, the newly created GOP is shorter than the standard size regular GOP.

Abstract: A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device.

Abstract: A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device.

Abstract: A system and method for editing a bitstream is provided. A first segment is cut from a first bitstream and a second segment is cut from a second bitstream. In cutting the segments from the bitstreams, first and last GOPs in the segments can be cut between frames in the GOP. The number of frames of the broken GOP is then compared to a pre-determined threshold value. If the number of frames of the broken GOP is less than or equal to the threshold value, the broken GOP is combined with a neighboring GOP. Therefore, the newly created GOP is longer than the standard size regular GOP. However, if the number of frames in the broken GOP is greater than the threshold value, a new GOP is created with the frames of the broken GOP. Therefore, the newly created GOP is shorter than the standard size regular GOP.

Abstract: The present invention provides a method for forming a CMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a substrate, a first gate positioned on the substrate being used to form a PMOS transistor of the CMOS transistor, and a second gate positioned on the substrate being used to form an NMOS transistor of the CMOS transistor. First spacers are formed on both lateral surfaces of the first gate and of the second gate. A first ion implantation process is performed to form a pair of first doped regions in the substrate, oppositely adjacent to the first gate, the pair of first doped regions to serve as heavy doped drain (HDD) of the PMOS transistor. Then the thickness of the first spacers is reduced. A second ion implantation process is performed to form a pair of second doped regions in the substrate, oppositely adjacent to the second gate, the pair of second doped regions to serve as the HDD of the NMOS transistor. Second spacers are then formed covering each first spacer.