Patents by Inventor Shih-Chun Lin

Shih-Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200168757
    Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 28, 2020
    Inventors: Yi-Chieh LIN, Shiuan-Leh LIN, Yung-Fu CHANG, Shih-Chang LEE, Chia-Liang HSU, Yi HSIAO, Wen-Luh LIAO, Hong-Chi SHIH, Mei-Chun LIU
  • Publication number: 20200135732
    Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Application
    Filed: December 26, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei PENG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Li-Chun TIEN, Pin-Dai SUE, Wei-Cheng LIN
  • Patent number: 10629693
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen Huang, Chung-Ting Ko, Hong-Hsien Ke, Chia-Hui Lin, Tai-Chun Huang
  • Patent number: 10617177
    Abstract: An apparatus for buffing a shoe part includes a housing adapted to be articulated around at least a portion of the footwear part. A rotating spindle is positioned in the housing and has a buffing surface for engagement with the footwear part. A carriage is slideably connected to the housing and holds the spindle such that the buffing surface can be moved closer to and further away from the footwear part. An actuator is in the housing and in contact with the carriage. The actuator applies force to the carriage to increase the force of the buffing surface onto the footwear part. A biasing member is in the housing and in contact with the carriage. The biasing member exerts force onto the carriage in a direction opposite the force exerted by the actuator.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: April 14, 2020
    Assignee: NIKE, Inc.
    Inventors: Dragan Jurkovic, Shih-Yuan Wu, Chia-Wei Chang, Wen-Ruei Chang, Chien-Chun Chen, Chang-Chu Liao, Chia-Hung Lin
  • Patent number: 10614766
    Abstract: A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: April 7, 2020
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Ren-Hong Luo, Shih-Chun Lin, Yung-Cheng Lin, Mu-Jung Chen
  • Patent number: 10612863
    Abstract: A pressing method and a finished product thereof are provided. The pressing method includes the steps of: providing a heat conductive base (1), and defining a pressed zone (10) on the heat conductive base (1); forming a plurality of penetrated holes (100) arranged with intervals in the pressed zone (10), and forming a pressed part (101) between any two of the adjacent penetrated holes (100); and processing a pressing and extruding operation to the pressed part (101) for allowing the pressed part (101) to be pressed and extruded so as to be extended and deformed towards the adjacent penetrated hole (100) for filling the penetrated hole (100).
    Type: Grant
    Filed: May 6, 2018
    Date of Patent: April 7, 2020
    Assignee: CHAUN-CHOUNG TECHNOLOGY CORP.
    Inventors: I-Yung Lin, Shih-Chun Sun
  • Publication number: 20200106155
    Abstract: A back cover includes a metal body having a first side, a second side, and a groove that is formed at the first side. The metal body further has a first radiator, a second radiator, and a ground radiator. The first radiator is disposed in the groove, and has a main portion and a support portion that cooperatively form a T-shape. The main portion includes a feeding end adjacent to a closed end of the groove. The second radiator is adjacently connected to the groove and is defined by the first and second sides, and an edge of the groove. The ground radiator is formed by a portion of the metal body excluding the first and second radiators. The second radiator and the support portion are connected to the ground radiator. The first and second radiators, and the ground radiator are serve as an antenna structure.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 2, 2020
    Applicant: Acer Incorporated
    Inventors: Shih-Ting Huang, Ching-Chi Lin, Chien-Wen Chen, Chuan-Chun Wang
  • Publication number: 20200098517
    Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.
    Type: Application
    Filed: May 21, 2019
    Publication date: March 26, 2020
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Publication number: 20200073507
    Abstract: A method for operating a handheld device, a handheld device, and a computer-readable recording medium thereof are provided. A first and a second sensors are disposed on a first and a second side of the handheld device, respectively. A processor of the handheld device is configured to determine the handheld device is in a left hand state or a right hand state according to a compared result between sensing data of the first and second sensors, and to display an operating interface corresponding to the right or left hand state on a display, where the compared result includes a force comparison between forces applied on the first and second sides of the handheld device, the first side corresponds to the right hand state, and the second side corresponds to the left hand state. Accordingly, a better operating experience for one hand can be provided.
    Type: Application
    Filed: September 3, 2018
    Publication date: March 5, 2020
    Applicant: HTC Corporation
    Inventors: Yu-Cheng Hung, Pei-Chun Tsai, Shih-Lung Lin
  • Publication number: 20200058544
    Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.
    Type: Application
    Filed: September 18, 2018
    Publication date: February 20, 2020
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Publication number: 20200058617
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
    Type: Application
    Filed: August 15, 2018
    Publication date: February 20, 2020
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih Han Huang, I-Nan Chen
  • Publication number: 20200027789
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Publication number: 20200027790
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Publication number: 20200013735
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. A second RDL structure is formed on and electrically coupled to an active surface of the semiconductor die. A ground layer is formed in the first RDL structure. A first molding compound layer is formed on the first RDL structure. A first antenna includes a first antenna element formed in the second RDL structure and a second antenna element formed on the first molding compound layer. Each of the first antenna element and the second antenna element has a first portion overlapping the semiconductor die as viewed from a top-view perspective.
    Type: Application
    Filed: June 25, 2019
    Publication date: January 9, 2020
    Applicant: MediaTek Inc.
    Inventors: Nai-Wei Liu, Yen-Yao Chi, Yeh-Chun Kao, Shih-Huang Yeh, Tzu-Hung Lin, Wen-Sung Hsu
  • Patent number: 10530044
    Abstract: A mobile device and antenna structure thereof are provided. An antenna structure is placed next to a pivot structure of the mobile device and a parasitic element is placed next to a high-frequency radiation element extending from a feeding element, so as to resonate with the high-frequency radiation element to generate a resonant mode for compensating the lack of a high-frequency bandwidth.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 7, 2020
    Assignee: Acer Incorporated
    Inventors: Shih-Ting Huang, Ching-Chi Lin, Chuan-Chun Wang, Ming-Ching Yen
  • Publication number: 20200006085
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Application
    Filed: April 12, 2019
    Publication date: January 2, 2020
    Inventors: Ya-Wen YEH, Yu-Tien SHEN, Shih-Chun HUANG, Po-Chin CHANG, Wei-Liang LIN, Yung-Sung YEN, Wei-Hao WU, Li-Te LIN, Pinyen LIN, Ru-Gun LIU
  • Publication number: 20200006514
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
  • Publication number: 20200006338
    Abstract: Exemplary embodiments of an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei PENG, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
  • Patent number: 10522542
    Abstract: Exemplary embodiments of an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
  • Patent number: 10509193
    Abstract: A driving mechanism includes a frame, a carrying base, and a drive module. The carrying base is disposed in the frame, and includes a carrying body, a first stop element and a second stop element. The carrying body is configured to carry an optical element. The first stop element is disposed on the carrying body, and configured to limit the range of motion of the carrying body in a first direction. The second stop element is disposed on the carrying body, and configured to limit the range of motion of the carrying body in the first direction. The driving module is disposed in the frame, and configured to move the carrying body relative to the frame. The first direction is parallel to the axis of the optical element, and the first stop element is closer to the top portion of the frame than the second stop element.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 17, 2019
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu