Abstract: Example computer-implemented methods, computer-readable media, and computer systems are described for accurate localization of wireless sensor devices in underground oil reservoirs. In some aspects, every sensor measures respective received magnetic field strengths (RMFSs) on a plurality of respective magnetic induction (MI) links and transmits the measured respective RMFSs to at least one anchor devices. A set of distances is determined from the measured respective RMFSs. The set of distances is processed through an ordered sequence of algorithms, namely weighted maximum likelihood estimation (WMLE), semi-definitec programming (SDP) relaxation, alternating direction augmented Lagrangian method (ADM), and conjugate gradient algorithm (CGA), to generate accurate localization of the wireless sensor devices in underground oil reservoirs.

Abstract: An apparatus, such as a network element, comprises a receiver to receive a plurality of packets from a plurality of traffic flows and a first non-transitory memory to form a first and second set of queues to store the plurality of packets from the plurality of traffic flows. One or more processors execute instructions stored in a second non-transitory memory to limit a rate of transfer of the plurality of packets that is output from the first set of queues to the second set of queues having a plurality of delays. A packet stored in the second set of queues is selected to be output based on a comparison of the plurality of delays.

Abstract: A method includes determining a number and placement of multiple controllers in a software defined network (SDN) such that each controller controls a different set of software controlled switches in the SDN and finding optimal forwarding paths for control traffic between the switches and controllers to minimize delay of control traffic over the software defined network.

Abstract: Example computer-implemented methods, computer-readable media, and computer systems are described for accurate localization of wireless sensor devices in underground oil reservoirs. In some aspects, every sensor measures respective received magnetic field strengths (RMFSs) on a plurality of respective magnetic induction (MI) links and transmits the measured respective RMFSs to at least one anchor devices. A set of distances is determined from the measured respective RMFSs. The set of distances is processed through an ordered sequence of algorithms, namely weighted maximum likelihood estimation (WMLE), semi-definite programming (SDP) relaxation, alternating direction augmented Lagrangian method (ADM), and conjugate gradient algorithm (CGA), to generate accurate localization of the wireless sensor devices in underground oil reservoirs.

Abstract: A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.

Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

Abstract: Example computer-implemented methods, computer-readable media, and computer systems are described for accurate localization of wireless sensor devices in underground oil reservoirs. In some aspects, every sensor measures respective received magnetic field strengths (RMFSs) on a plurality of respective magnetic induction (MI) links and transmits the measured respective RMFSs to at least one anchor devices. A set of distances is determined from the measured respective RMFSs. The set of distances is processed through an ordered sequence of algorithms, namely weighted maximum likelihood estimation (WMLE), semi-definitec programming (SDP) relaxation, alternating direction augmented Lagrangian method (ADM), and conjugate gradient algorithm (CGA), to generate accurate localization of the wireless sensor devices in underground oil reservoirs.

Abstract: A method includes obtaining traffic statistics of accepted hybrid traffic at a controller of a software defined network that includes multiple local switches coupled by links, calculating an end to end delay associated with the accepted hybrid traffic, determining network stability thresholds from each local switch as a function of network congestion, determining an adjusted rate decision policy as a function of the end to end delay and the network stability thresholds, the adjusted rate decision policy for use by an edge switch to determine whether or not to accept offered traffic loads.

Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

Abstract: A network element (NE) comprising a receiver configured to receive packets from a plurality of flows, and a processor coupled to the receiver and configured to perform classification on the plurality of flows according to arrivals of the packets to classify the plurality of flows into a heavy-tailed (HT) class and a light-tailed (LT) class assign scheduling weights to the plurality of flows according to the classification, and select a scheduling policy to forward the packets of the plurality of flows according to the scheduling weights.

Abstract: Example computer-implemented methods, computer-readable media, and computer systems are described for providing communication protocol architecture or framework for magnetic induction (MI)-based communications in wireless underground sensor networks (WUSNs), for example, in underground oil reservoirs. In some aspects, environment information of an underground region that affects the transmission qualities of MI communications is evaluated. A protocol stack is identified. The protocol stack includes a number of layers for MI communications among a number of sensors in a WUSN in the underground region. A cross-layer framework and the distributed protocol are built to jointly optimize communication functionalities of the plurality of layers based on the evaluation.

Abstract: An apparatus is configured to perform a method for in-band control traffic load balancing in a software defined network (SDN). The method includes generating one or more Markovian traffic statistics for one or more control traffic and data traffic statistics. The method also includes constructing a queueing network system based on the Markovian traffic statistics. The method further includes determining a control traffic load balancing problem based on the Markovian traffic statistics. In addition, the method includes solving the control traffic load balancing problem using one or more primal-dual update rules.

Abstract: A method and an apparatus that allocate controllers in an SDN are described. The SDN may comprise a plurality of switches, each switch having a selection likelihood and one or more assignment likelihoods. Possible values of the selection likelihood and the assignment likelihoods of each switch may be identified subject to allocation constraint imposed on one or more controllers of the SDN. A set of values from the possible values of the selection likelihood and the assignment likelihoods of each switch can be selected. The set of values selected can be rounded to integer values respectively. And the controllers of the SDN can be allocated based on the integer values.

Abstract: A clock data recovery circuit including a recovery unit and a loop control unit is provided. The recovery unit generates a recovery clock signal according to an original data signal. The recovery unit locks a frequency of the recovery clock signal to a correction frequency through a first loop, and locks the frequency of the recovery clock signal to a sampling frequency through a second loop. The correction frequency is smaller than the sampling frequency. The recovery unit adjusts the frequency of the recovery clock signal according to a reference clock signal and a first dividing signal in the first loop. The loop control unit switches the recovery unit to the first loop or the second loop according to a frequency difference between the reference clock signal and a second dividing signal.

Abstract: A clock data recovery circuit including a recovery unit and a loop control unit is provided. The recovery unit generates a recovery clock signal according to an original data signal. The recovery unit locks a frequency of the recovery clock signal to a correction frequency through a first loop, and locks the frequency of the recovery clock signal to a sampling frequency through a second loop. The correction frequency is smaller than the sampling frequency. The recovery unit adjusts the frequency of the recovery clock signal according to a reference clock signal and a first dividing signal in the first loop. The loop control unit switches the recovery unit to the first loop or the second loop according to a frequency difference between the reference clock signal and a second dividing signal.

Abstract: A multi-phase clock generator including a first delay locked loop, a reference signal generator and a second delay locked loop is provided. The first delay locked loop generates 2N phase clock signals according to an input clock signal, so as to equally divide a clock period of the input clock signal into 2N predetermined phases, where N is a positive integer. The reference signal generator selects two phase clock signals according to a digital signal, and adjusts an output ratio of the two phase clock signals in 2M clock periods to serve as a reference clock signal. The second delay locked loop delays a first phase clock signal according to a phase difference between the reference clock signal and an output clock signal. In this way, each predetermined phase is further equally divided into 2M sub-phases, so that the multi-phase clock generator has 2(N+M) phase selections.

Abstract: The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.

Abstract: A multi-phase clock generator including a first delay locked loop, a reference signal generator and a second delay locked loop is provided. The first delay locked loop generates 2N phase clock signals according to an input clock signal, so as to equally divide a clock period of the input clock signal into 2N predetermined phases, where N is a positive integer. The reference signal generator selects two phase clock signals according to a digital signal, and adjusts an output ratio of the two phase clock signals in 2M clock periods to serve as a reference clock signal. The second delay locked loop delays a first phase clock signal according to a phase difference between the reference clock signal and an output clock signal. In this way, each predetermined phase is further equally divided into 2M sub-phases, so that the multi-phase clock generator has 2(N+M) phase selections.

Abstract: A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.

Abstract: A spread-spectrum generator is provided. The spread-spectrum generator includes a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time, and thereby generate a delay signal. The control module is coupled to the delay module for detecting a first edge of the delay signal, and thereby generating the first control signal. Accordingly, the spread-spectrum generator can spread the frequency of the input signal by delaying the input signal by various delay time, and the spread-spectrum generator can also reduce electromagnetic interference (EMI).