Abstract: A multi-chip integrated package design system includes a model analysis, a 3D model analysis and an electrical simulation. The model analysis obtains a pin connection mode of the designed circuit according to a designed circuit, obtains at least one conductive layer of the designed circuit according to a layer stackup, selects a transmission line model that meets the pin connection mode and at least one conductive layer, substitutes the layer stackup and a design rule into the selected transmission line model to generate an equivalent circuit, generates a corresponding relationship according to the equivalent circuit, and obtains the transmission line length corresponding to a parameter design target according to the corresponding relationship. The 3D model analysis constructs a 3D model of the designed circuit according to the obtained the transmission line length. The electrical simulation determines whether the characteristic parameter of the 3D model meets the parameter design target.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A light-emitting module of an illuminated keyboard includes a reflector plate, a light guiding plate, a light shielding plate, a base plate, a thin film circuit board, and a light-emitting element. The light guiding plate is disposed on the reflector plate. The light shielding plate is disposed on the light guiding plate and includes a through hole and a first light-passing hole that is spaced apart from the through hole. The base plate is disposed on the light shielding plate and includes an accommodating hole that is aligned with the through hole and a second light-passing hole that is spaced part from the accommodating hole and that is aligned with the first light-passing hole. The thin film circuit board is disposed on the base plate. The light-emitting element is disposed on the thin film circuit board and extends into the accommodating hole.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A circuit board structure is provided. The circuit board structure includes a substrate, a solder mask coupler, a supporter, and a chip. The substrate has a conductive structure. The solder mask coupler is disposed on the substrate. The supporter contacts the solder mask coupler, and the supporter is fixed on the substrate via the solder mask coupler. The chip is disposed on the substrate, and the chip is electrically connected with the conductive structure.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A power design architecture including a power supply circuit, a power wiring, at least one chip, a power ring, and a first reference conductor is provided. The power wiring is connected to the power supply circuit. The power ring is disposed around the chip and electrically connected to the chip and the power wiring. The first reference conductor is electrically connected to the chip. Low self-impedance is maintained at any position of the power ring.

Abstract: An electronic device includes a substrate, an upper conductive layer, and a lower conductive layer. The substrate has a plurality of inner vias and has an upper surface and a lower surface. The upper conductive layer includes an upper ground trace and an upper signal pad disposed on the upper surface. The upper ground trace is electrically connected to the ground vias and has an upper hollow portion exposing a part of the upper surface. The upper signal pad is disposed on the part of the upper surface exposed by the upper hollow portion and electrically connected to the signal via. The lower conductive layer includes a lower ground trace and a lower signal pad disposed on the lower surface. The lower conductive trace is electrically connected to the ground vias and has a lower hollow portion exposing a part of the lower surface. The lower signal pad is disposed on the part of the lower surface exposed by the lower hollow portion and electrically connected to the signal via.

Abstract: An electronic device having a substrate includes a substrate and at least one outer layer. The substrate has a plurality of first vias. The outer layer has a plurality of second vias. The outer layer is disposed on a side of the substrate. The first vias have a larger distribution density or quantity than the second vias so that a portion of the first vias are electrically connected to the second vias, and a portion of the first vias are electrically floating.

Abstract: An electronic device includes a substrate, an upper conductive layer, and a lower conductive layer. The substrate has a plurality of inner vias and has an upper surface and a lower surface. The upper conductive layer includes an upper ground trace and an upper signal pad disposed on the upper surface. The upper ground trace is electrically connected to the ground vias and has an upper hollow portion exposing a part of the upper surface. The upper signal pad is disposed on the part of the upper surface exposed by the upper hollow portion and electrically connected to the signal via. The lower conductive layer includes a lower ground trace and a lower signal pad disposed on the lower surface. The lower conductive trace is electrically connected to the ground vias and has a lower hollow portion exposing a part of the lower surface. The lower signal pad is disposed on the part of the lower surface exposed by the lower hollow portion and electrically connected to the signal via.

Abstract: An electronic device includes a substrate, an outer layer, a conductive line layer, and a switchable circuit chip. The substrate has a plurality of having a plurality of first vias. The outer layer is disposed on a side of the substrate and has a plurality of second vias. The first vias have a larger distribution density or quantity than the second vias, so that a part of the first vias are electrically connected to the second vias, and another part of the first vias are electrically floating. The conductive line layer is disposed on the outer layer and has a plurality of conductive traces. The conductive traces are electrically connected to the second vias. The switchable circuit chip is electrically connected to the first vias. The conductive traces are electrically connected to the switchable circuit chip.

Abstract: A circuit structure includes a substrate integrated waveguide, a substrate disposed on the substrate integrated waveguide, a waveguide signal feeding element and a ring-shaped conductive element. The substrate integrated waveguide includes another substrate having a waveguide transmitting region, two conductive layers disposed on this substrate and covering the waveguide transmitting region, and at least one waveguide conductive element passing through this substrate and electrically connected to the two conductive layers. The at least one waveguide conductive element surrounds the waveguide transmitting region. One of the conductive layers is located between the two substrates. The waveguide signal feeding element passes through one substrate and one conductive layer between the substrates, and the waveguide signal feeding element extends to the waveguide transmitting region. The waveguide signal feeding element is electrically insulated from one conductive layer.

Abstract: A fabrication method of a flexible electronic package device including the following steps is provided. A tolerable bending radius of the flexible electronic package device is obtained. A minimum surface curvature radius of a selected portion of an applied carrier is obtained. A relationship of the tolerable bending radius being smaller than the minimum surface curvature radius is ensured. The flexible electronic package device is disposed on the selected portion.

Abstract: A fabrication method of a flexible electronic package device including the following steps is provided. A tolerable bending radius of the flexible electronic package device is obtained. A minimum surface curvature radius of a selected portion of an applied carrier is obtained. A relationship of the tolerable bending radius being smaller than the minimum surface curvature radius is ensured. The flexible electronic package device is disposed on the selected portion.

Abstract: A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.

Abstract: A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.

Abstract: An electronic device having a substrate includes a substrate and at least one outer layer. The substrate has a plurality of first vias. The outer layer has a plurality of second vias. The outer layer is disposed on a side of the substrate. The first vias have a larger distribution density or quantity than the second vias so that a portion of the first vias are electrically connected to the second vias, and a portion of the first vias are electrically floating.

Abstract: A reconfigurable data bus system comprises a driver, a receiver, a data bus and a detector. The driver stores an electrical parameter data base. The electrical parameter data base includes a plurality of different signal-to-ground ratios and a plurality of signal quality parameters corresponding to the signal-to-ground ratios. The data bus includes a plurality of signal lines electrically connected between the driver and the receiver. The detector is electrically connected to the data bus and the driver. The detector is configured to detect a current signal quality parameter of the data bus and transmit the current signal quality parameter to the driver. The driver is selectively reconfigured a current signal-to-ground ratio according to a current signal quality parameter of the data bus and the electrical parameter database.

Abstract: A circuit structure includes a substrate integrated waveguide, a substrate disposed on the substrate integrated waveguide, a waveguide signal feeding element and a ring-shaped conductive element. The substrate integrated waveguide includes another substrate having a waveguide transmitting region, two conductive layers disposed on this substrate and covering the waveguide transmitting region, and at least one waveguide conductive element passing through this substrate and electrically connected to the two conductive layers. The at least one waveguide conductive element surrounds the waveguide transmitting region. One of the conductive layers is located between the two substrates. The waveguide signal feeding element passes through one substrate and one conductive layer between the substrates, and the waveguide signal feeding element extends to the waveguide transmitting region. The waveguide signal feeding element is electrically insulated from one conductive layer.

Abstract: A reconfigurable data bus system comprises a driver, a receiver, a data bus and a detector. The driver stores an electrical parameter data base. The electrical parameter data base includes a plurality of different signal-to-ground ratios and a plurality of signal quality parameters corresponding to the signal-to-ground ratios. The data bus includes a plurality of signal lines electrically connected between the driver and the receiver. The detector is electrically connected to the data bus and the driver. The detector is configured to detect a current signal quality parameter of the data bus and transmit the current signal quality parameter to the driver. The driver is selectively reconfigured a current signal-to-ground ratio according to a current signal quality parameter of the data bus and the electrical parameter database.