Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.

Abstract: A semiconductor device is provided. The semiconductor device includes at least one first die, a rib structure enclosing the at least one first die, and a molding layer covering the at least one first die. The rib structure is formed of a first material and the molding layer is formed of a second material. A Young's modulus of the first material is larger than a Young's modulus of the second material.

Abstract: A circuit structure includes an annular conductor, a conductive via and at least one extension conductor. The annular conductor extends along a direction. The conductive via is disposed in the annular conductor and extending along the direction. The at least one extension conductor is electrically connected to at least one end of the annular conductor and extending toward the conductive via.

Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.

Abstract: A semiconductor substrate assembly includes a semiconductor material layer, a first isolation layer, a second isolation layer, a first conductive pillar, and a second conductive pillar. The semiconductor material layer has a first surface and a second surface opposite to the first surface. The first isolation layer is located on the first surface of the semiconductor material layer. The second isolation layer is located on the second surface of the semiconductor material layer. The first conductive pillar, supplied with a first voltage, penetrates the semiconductor material layer, the first isolation layer, and the second isolation layer. The second conductive pillar is supplied with to a second voltage, and a part of the second conductive pillar is formed in the second isolation layer, the second conductive pillar penetrates the second isolation layer and touches the second surface of the semiconductor material layer.

Abstract: A via structure includes a ground conductor, a floated conductor and a signal conductor. The ground conductor is electrically coupled to a reference potential. The floated conductor is electrically insulated from the ground conductor. The signal conductor is located between and insulated from the ground conductor and the floated conductor.

Abstract: A via structure includes a ground conductor, a floated conductor and a signal conductor. The ground conductor is electrically coupled to a reference potential. The floated conductor is electrically insulated from the ground conductor. The signal conductor is located between and insulated from the ground conductor and the floated conductor.

Abstract: The disclosure provides a manufacturing method for a circuit board having a via and including a substrate, a ground conductor, a floated conductor and a signal conductor. The substrate includes a second sheet layer, a second ground layer, a core layer, a first ground layer and a first sheet layer that are stacked in sequence from bottom to top. The ground conductor penetrates through the core layer and is electrically coupled to the first ground layer and the second ground layer. The floated conductor penetrates through the core layer and is electrically insulated from the first ground layer, the second ground layer and the ground conductor. The signal conductor penetrates through the substrate, being located between the ground conductor and the floated conductor, and insulated from the first ground layer, the second ground layer, the ground conductor and the floated conductor.

Abstract: The disclosure provides a manufacturing method for a circuit board having a via and including a substrate, a ground conductor, a floated conductor and a signal conductor. The substrate includes a second sheet layer, a second ground layer, a core layer, a first ground layer and a first sheet layer that are stacked in sequence from bottom to top. The ground conductor penetrates through the core layer and is electrically coupled to the first ground layer and the second ground layer. The floated conductor penetrates through the core layer and is electrically insulated from the first ground layer, the second ground layer and the ground conductor. The signal conductor penetrates through the substrate, being located between the ground conductor and the floated conductor, and insulated from the first ground layer, the second ground layer, the ground conductor and the floated conductor.

Abstract: A semiconductor substrate assembly is proposed. The semiconductor interposer comprises a substrate having a first surface and a second surface opposite to the first surface, a first conductive pad, a second conductive pad and a conductive pillar. The first conductive pad is formed at a predetermined location of the first surface of the substrate. The second conductive pad is formed at a predetermined location of the second surface of the substrate as compared with the position of the first conductive pad. The conductive pillar is formed in the substrate and contacts with one of the first conductive pad and the second conductive pad.

Abstract: A chip stacking structure including a plurality of microbump structures, a plurality of first substrates, at least one first space layer, a plurality of second substrates and at least one second space layer is provided. The first substrates are stacked upon each other by a portion of the microbump structures, and each of the first substrates includes at least one first redistribution layer. The first space layer is located between the stacked first substrates. The second substrates are stacked on at least one of the first substrates by another portion of the microbump structures, and each of the second substrates includes at least one second redistribution layer. The second space layer is located between the stacked first and second substrates. The first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.

Abstract: A semiconductor substrate assembly includes a semiconductor material layer, a first isolation layer, a second isolation layer, a first conductive pillar, and a second conductive pillar. The semiconductor material layer has a first surface and a second surface opposite to the first surface. The first isolation layer is located on the first surface of the semiconductor material layer. The second isolation layer is located on the second surface of the semiconductor material layer. The first conductive pillar, supplied with a first voltage, penetrates the semiconductor material layer, the first isolation layer, and the second isolation layer. The second conductive pillar is supplied with to a second voltage, and a part of the second conductive pillar is formed in the second isolation layer, the second conductive pillar penetrates the second isolation layer and touches the second surface of the semiconductor material layer.

Abstract: An interconnection structure is disposed between a first conductive layer and a second conductive layer substantially parallel to each other. The conductive layer includes a signal trace. The interconnection structure includes a conductor pillar and a shielding wall pillar. The conductor pillar goes through between the two conductive layers and is electrically connected to the signal trace of the first conductive layer. The shielding wall pillar is also disposed between the two conductive layers and located at a portion of an external region surrounding the conductor pillar and electrically coupled to the conductor pillar. The conductor pillar and the shielding wall pillar are disposed in pair or in group. The shielding wall pillar with a shape different from that of the conductor pillar would make the conductor pillar serve as a connection with a designed impedance and the capability of controlling impedance based on the special shape design thereof.

Abstract: A chip stacking structure including a plurality of microbump structures, a plurality of first substrates, at least one first space layer, a plurality of second substrates and at least one second space layer is provided. The first substrates are stacked upon each other by a portion of the microbump structures, and each of the first substrates includes at least one first redistribution layer. The first space layer is located between the stacked first substrates. The second substrates are stacked on at least one of the first substrates by another portion of the microbump structures, and each of the second substrates includes at least one second redistribution layer. The second space layer is located between the stacked first and second substrates. The first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.

Abstract: A semiconductor substrate assembly is proposed. The semiconductor interposer comprises a substrate having a first surface and a second surface opposite to the first surface, a first conductive pad, a second conductive pad and a conductive pillar. The first conductive pad is formed at a predetermined location of the first surface of the substrate. The second conductive pad is formed at a predetermined location of the second surface of the substrate as compared with the position of the first conductive pad. The conductive pillar is formed in the substrate and contacts with one of the first conductive pad and the second conductive pad.

Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.

Abstract: The disclosure provides a capacitor structure. A first dielectric layer is disposed over the first electrode layer. A second electrode layer is disposed over the first dielectric layer. At least one of the first electrode layer and the second electrode layer has a peak-valley like structure to create at least two different gap distances therebetween, thereby providing parallel combinations of at least two different capacitances.

Abstract: An interconnection structure is disposed between a first conductive layer and a second conductive layer substantially parallel to each other. The conductive layer includes a signal trace. The interconnection structure includes a conductor pillar and a shielding wall pillar. The conductor pillar goes through between the two conductive layers and is electrically connected to the signal trace of the first conductive layer. The shielding wall pillar is also disposed between the two conductive layers and located at a portion of an external region surrounding the conductor pillar and electrically coupled to the conductor pillar. The conductor pillar and the shielding wall pillar are disposed in pair or in group. The shielding wall pillar with a shape different from that of the conductor pillar would make the conductor pillar serve as a connection with a designed impedance and the capability of controlling impedance based on the special shape design thereof.

Abstract: A stepwise capacitor structure includes at least one stepwise conductive layer. The stepwise capacitor represents a feature of multiple capacitors. When currents flow through the stepwise capacitor, different current paths are presented in between an upper conductor and a bottom conductor of the stepwise capacitor in response to different current frequency; different inductor is induced in each path and decoupled by a stepwise capacitor structure as disclosed herein.

Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.