Abstract: A throttle control method for a mobile device include collecting input data, generating a first set of user experience indices according to the input data, and checking whether a user experience index of the first set of user experience indices satisfies a UEI threshold. The input data includes common information data, current configuration data and a plurality of throttle control parameters. Each user experience index of the first set of user experience indices is corresponding to at least one of throttle control parameter of the plurality of throttle control parameters.

Abstract: In a method of cleaning a lithography system, during idle mode, a stream of air is directed, through a first opening, into a chamber of a wafer table of an EUV lithography system. One or more particles is extracted by the directed stream of air from surfaces of one or more wafer chucks in the chamber of the wafer table. The stream of air and the extracted one or more particle are drawn, through a second opening, out of the chamber of the wafer table.

Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

Abstract: In one example in accordance with the present disclosure, an electronic device is described. The example electronic device includes a microphone device to record a tracheal sound. The example electronic device also includes an oral expiratory flow sensor to measure oral expiratory flow contents. The example electronic device further includes a processor to determine a health condition based on the tracheal sound and the oral expiratory flow contents.

Abstract: A testing method includes the following operations: performing a place and route procedure according to a netlist file corresponding to a chip to generate first layout data; determining whether to replace a flip-flop circuit in the chip with a gated flip-flop circuit according to the first layout data to generate second layout data; and running a test on the chip according to the second layout data.

Abstract: A testing method includes the following operations: performing a place and route procedure according to a netlist file corresponding to a chip, in order to generate first layout data; determining whether to replace a flip-flop circuit in the chip with a gated flip-flop circuit according to the first layout data, in order to generate second layout data; and running a test on the chip according to the second layout data.

Abstract: An integrated circuit (IC) and a method for operating the IC are provided. The IC comprises a device under test and a first heater. The first heater is located at a first side of the device and provides heat to control a temperature of the device. The first heater comprises a semiconductor device having a first doped region and a second doped region having a conductivity type opposite to that of the first doped region, the first doped region interfacing with the second doped region.

Abstract: An integrated circuit (IC) and a method for operating the IC are provided. The IC comprises a device under test and a first heater. The first heater is located at a first side of the device and provides heat to control a temperature of the device. The first heater comprises a semiconductor device having a first doped region and a second doped region having a conductivity type opposite to that of the first doped region, the first doped region interfacing with the second doped region.

Abstract: One or more systems and methods for a cell based hybrid resistance and capacitance (RC) extraction are provided. The method includes generating a layout for a semiconductor arrangement, performing a three-dimensional (3D) RC extraction on a target unit cell to obtain a 3D RC result including a coupling capacitance between unit cells, generating a 3D RC netlist based upon the 3D RC result, performing a 2.5 dimensional (2.5D) RC extraction on a peripheral cell to obtain a 2.5D RC netlist, and combining the 3D RC netlist with the 2.5D RC netlist to create a hybrid RC netlist for the layout. In some embodiments, the hybrid RC netlist is generated by stitching the coupling capacitance for at least one of the target unit cell, a repeating unit cell, or the peripheral cell together. In some embodiments, the 3D RC result for the target unit cell is stitched to the repeating unit cell.

Abstract: A method for creating web programs and corresponding table interfaces according to column comments is revealed. The method features on that codes predefined are stored in the comment of each column in a table respectively and each code corresponds to a function. Then attribute data and the code of each column are obtained by metadata of a relational database. A program required for retrieving and storing data in the relational database is produced according to the attribute data and to the code. Thus a corresponding web code file is created. Finally, a table interface and a program for processing web pages of each column corresponding to the function are created by a web editing system according to the web code file. Thereby web application development is dramatically accelerated.

Abstract: A power management method includes providing status information of an external module to an intermediary module for updating status data; accessing updated status data via the intermediary module; determining a power value according to the updated status data; determining power allocation according to at least the power value; and providing power to the external module according to the power allocation.

Abstract: The settings related to form fields now are unable to be set dynamically according to attributes of a table. The settings related to form fields include length of form fields, validation rule of form filed (such as length of input character or whether the input character is a not null parameter, etc.), and presentation of form fields (such as check box or calendar time selection interface). The present invention uses result set metadata of a relational database to get the attributes. Thus a form interface includes form fields corresponding to the attributes. And the presentation of the form fields can be determined by the corresponding attribute parameters. Moreover, whether data format is correct is checked by a form validation program according to data user input into the form field. Thereby development workflow can be simplified and development time can be shortened for web developers and program designers.

Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

Abstract: Embodiments of system and methods for managing memory cells are disclosed, where a memory priority map is generated based on at least one testing procedure, and memory cells of a memory device are allocated to at least one application executed in a computing system by the memory priority map and defined allocating regulations. Further, whenever a fresh memory testing procedure is executed, the memory priority map is updated.

Abstract: The settings related to form fields now are unable to be set dynamically according to attributes of a table. The settings related to form fields include length of form fields, validation rule of form filed (such as length of input character or whether the input character is a not null parameter, etc.), and presentation of form fields (such as check box or calendar time selection interface). The present invention uses result set metadata of a relational database to get the attributes. Thus a form interface includes form fields corresponding to the attributes. And the presentation of the form fields can be determined by the corresponding attribute parameters. Moreover, whether data format is correct is checked by a form validation program according to data user input into the form field. Thereby development workflow can be simplified and development time can be shortened for web developers and program designers.

Abstract: An integrated circuit design method comprises extracting parallel-connected parameters associated with circuit components of an integrated circuit (IC) based on a determination that the circuit components are connected in parallel. The method also comprises generating a parallel netlist that describes the circuit components, the parallel netlist comprising the parallel-connected parameters. The parallel-connected parameters are taken into consideration by a simulation that determines the performance capabilities of the IC.

Abstract: One or more systems and methods for a cell based hybrid resistance and capacitance (RC) extraction are provided. The method includes generating a layout for a semiconductor arrangement, performing a 3D RC extraction on a target unit cell to obtain a 3D RC result including a coupling capacitance between unit cells, generating a 3D RC netlist based upon the 3D RC result, performing a 2.5D RC extraction on a peripheral cell to obtain a 2.5D RC netlist, and combining the 3D RC netlist with the 2.5D RC netlist to create a hybrid RC netlist for the layout. In some embodiments, the hybrid RC netlist is generated by stitching the coupling capacitance for at least one of the target unit cell, a repeating unit cell, or the peripheral cell together. In some embodiments, the 3D RC result for the target unit cell is stitched to the repeating unit cell.

Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.