Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

Abstract: An integrated circuit design method comprises extracting parallel-connected parameters associated with circuit components of an integrated circuit (IC) based on a determination that the circuit components are connected in parallel. The method also comprises generating a parallel netlist that describes the circuit components, the parallel netlist comprising the parallel-connected parameters. The parallel-connected parameters are taken into consideration by a simulation that determines the performance capabilities of the IC.

Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

Abstract: Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.

Abstract: Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.

Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

Abstract: The present invention relates to the structure of eye glasses. More specifically, the frame has embedded clamps on the outside part of the front. Embedded clamps can be displaced inward or outward along the outside part of the front. When embedding the lens into the lens assembly area which consists of the inner part, upper part, and outside part of the front, the embedded clamps can be pushed outward. Upon embedding the lens in the front, the embedded clamps can be pushed inward, by this way, the front and back of the embedded clamps can clamp the front, thereby fixing the lens.

Abstract: The patent relates to the structure of sports eyeglasses, which includes frames and rims. The frames contains upper and lower frame (together as combined frame) and temple attached to two sides of the combined frame. The rims join with the combined frame. The rims has 2 rim holes designed to allow the lens to fit. The width of the upper frame and the lower frame increase from the bridge to the sides of the frame, therefore the upper frame and the lower frame can be combined with the outer frame. The outer section of the upper frame is covered by the protective pad. The inner frame separates with the upper frame, and there are screw holes at the disconnected segments. Screws can pass though the screw holes to lock the disconnected segments of the upper frame and the inner frame together. As a result, it is easy to insert the lenses within the rim. By locking the frames with the rims, a pair of sports eyeglasses is easily assembled.

Abstract: An error correction method for correcting an first ECC code from a storage unit, comprising: (a) marking at least a first part of the first ECC code according to a correction result generated by correcting error of the first ECC code, to generate a first error correction reference information; and (b) marking at least a second part of the first ECC code according to the first error correction reference information to generate a second error correction reference information.

Abstract: The invention provides a method for data recovery. In one embodiment, a memory comprises a plurality of pages for data storage. First, first data is obtained from a host. A first page for storing the first data is then selected from the pages of the memory. A start page link indicating the first page is then stored in the memory. The first data, a first page link indicating a next page, and first FTL fragment data corresponding to the first page are then written into the first page. Next data is then obtained from the host. The next data, a next page link indicating a subsequent page, and FTL fragment data corresponding to the next page are written into the next page.

Abstract: The invention provides a method for reading information of an optical data storage medium. First, one sector of the optical data storage medium is obtained. The sector is then decoded to check if the sector is reliable. When the sector is not reliable, a data rescue process referring to spec-defined or pre-defined information of the physical specification of the sector is performed in order to obtain disc fundamental information of the optical data storage medium.

Abstract: A buffer management method operates by receiving a read command, wherein the read command comprises a read destination address for designating an associated area of a storage media; receiving write commands, wherein each of the write command comprises a data block and a write destination address for designating an associated location of the storage media to store the data block; buffering the data blocks of the write commands in a buffer; generating a latest list, wherein the latest list comprises a plurality of buffer indexes indicating buffer areas for storing the data blocks associated with the latest certain amount of received write commands; and determining whether the read destination address of the read command is associate with the latest list.

Abstract: A controller for recovering disc management information is provided. The controller controls a pickup head unit to search the TDMAs for readable disc management information which is included in an in-use TDMA of the TDMAs; then determines whether a piece of information associated with an inconsistency flag of the readable disc management information is reliable. When the controller detects that the piece of information is unreliable, the controller determines at least a detection condition according to the information which is included in the readable disc management information and the in-use TDMA, and controls the pickup head unit to detect the recording medium to determine an update on the piece of information associated with the inconsistency flag under at least a detection condition. The controller generates update disc management information according to the readable disc management information and the update on the piece of information associated with the inconsistency flag.

Abstract: An optical disc drive is provided, mainly comprising a buffer, a processor and a driving module for accessing an optical disc. The optical disc drive receives a plurality of write commands. Each write command comprises a data block and a destination address. The buffer buffers data blocks to be recorded to the optical disc with corresponding write commands in either a random mode or a sequential mode. The processor schedules a recording operation based on the write commands, and selectively switches the buffer to the random mode or to the sequential mode based on arrangements of data blocks buffered in the buffer. The driving module is controlled by the processor to perform the recording operation, whereby the data blocks are recorded to the optical disc when a start recording condition is met. Specifically, the start recording condition varies with the random or sequential modes.

Abstract: The invention provides a method for data recovery. In one embodiment, a memory comprises a plurality of pages for data storage. First, first data is obtained from a host. A first page for storing the first data is then selected from the pages of the memory. A start page link indicating the first page is then stored in the memory. The first data, a first page link indicating a next page, and first FTL fragment data corresponding to the first page are then written into the first page. Next data is then obtained from the host. The next data, a next page link indicating a subsequent page, and FTL fragment data corresponding to the next page are written into the next page.

Abstract: A controller for recovering disc management information is provided. The controller controls a pickup head unit to search the TDMAs for readable disc management information which is included in an in-use TDMA of the TDMAs; then determines whether a piece of information associated with an inconsistency flag of the readable disc management information is reliable. When the controller detects that the piece of information is unreliable, the controller determines at least a detection condition according to the information which is included in the readable disc management information and the in-use TDMA, and controls the pickup head unit to detect the recording medium to determine an update on the piece of information associated with the inconsistency flag under at least a detection condition. The controller generates update disc management information according to the readable disc management information and the update on the piece of information associated with the inconsistency flag.

Abstract: A method for recovering disc management information of a recording medium. (a) When the recording medium is not closed, a readable TDMS which is included in an in-use TDMA of TDMAs of the recording medium and is readable is searched for. (b) It is determined whether a piece of information associated with an inconsistency flag of the readable TDMS is reliable. (c) If the associated piece of information is unreliable, at least a detection condition is determined according to the information included in the readable TDMS and the in-use TDMA. (d) A detection procedure, constrained by the at least the detection condition, is performed on the recording medium for determining an update on the piece of information associated with the inconsistency flag. (e) An update TDMS is generated according to the readable TDMS and the update on the piece of information associated with the inconsistency flag.

Abstract: A random access control method is provided, implemented in an optical disc drive for recording data to an optical disc. In the optical disc drive, a buffer stores a plurality of write commands each associated with a data block bound to a destination address. A processor controls the buffer to build a disc write task from the write commands in which addresses are organized in order. A drive unit is controlled by the processor, performing a recording operation to record the data blocks to the optical disc according to the disc write task; wherein the processor further controls the drive unit to verify the recorded data blocks after completing the recording operation.

Abstract: An error correction method for correcting an first ECC code from a storage unit, comprising: (a) marking at least a first part of the first ECC code according to a correction result generated by correcting error of the first ECC code, to generate a first error correction reference information; and (b) marking at least a second part of the first ECC code according to the first error correction reference information to generate a second error correction reference information.