Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, successive approximation register (SAR) circuitries, and noise shaping circuitries. The capacitor arrays sample an input signal by turns, in order to provide a sampled input signal. The SAR circuitries perform an analog-to-digital conversion by turns according to a combination of the sampled input signal, a first residue signal, and a second residue signal, in order to generate digital outputs. The noise shaping circuitries receive a corresponding residue signal of the first residue signal the second residue signal in response to the analog-to-digital conversion, and to shape and transmit the corresponding residue signal to the SAR circuitries.

Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. When a first capacitor array of the capacitor arrays samples an input signal in a first phase, a second capacitor array of the capacitor arrays outputs the input signal sampled in a second phase as a sampled input signal. The SAR circuitry performs an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor that stores the residue signal generated in the second phase. The switching circuitry couples the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes the following steps: controlling the DAC not to receive the output of the quantizer; controlling the SDM to stop receiving signals; inputting a test signal to the DAC; converting the output of the loop filter to a digital signal; comparing the digital signal with a preset value; and adjusting the loop filter according to the result of comparing the digital signal and the preset value.

Abstract: A switched capacitor circuit includes a first capacitor, a second capacitor, and a switching circuit. The first capacitor is configured to receive a first signal. The second capacitor is configured to receive a second signal. The switching circuit is configured to selectively couple the first capacitor and the second capacitor to an input terminal of a quantizer according to at least one clock signal. In a first configuration of the switching circuit, the first capacitor is configured to store the first signal, and the second capacitor is configured to store the second signal. In a second configuration of the switching circuit, the first capacitor and the second capacitor are stacked in series, in order to transmit a combination of the first signal and the second signal to the input terminal of the quantizer.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are disclosed. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC), and the loop filter includes a resonator. The correction circuit includes a memory and a control circuit. The memory stores multiple program instructions. The control circuit executes the program instructions to correct the SDM. The correction procedure of the SDM includes the following steps: inputting a test signal to the SDM; obtaining a signal characteristic value of an output signal of the SDM; and adjusting the resonator according to the signal characteristic value.

Abstract: This invention discloses a successive approximation register analog-to-digital converter (SAR ADC) and a control circuit thereof. The SAR ADC includes a comparator, a switched-capacitor digital-to-analog converter (DAC), and a control circuit. The switched-capacitor DAC includes a capacitor and a driving circuit that is electrically connected to the capacitor. The driving circuit comprises a P-type MOSFET and an N-type MOSFET, and the gates of the two MOSFETs are not electrically connected. The P-type MOSFET is controlled by a first control signal, and the N-type MOSFET is controlled by a second control signal. The control circuit controls the voltage at one end of the capacitor to switch from a high voltage level to a low voltage level by controlling the rising edge of the first control signal to lead the rising edge of the second control signal.

Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, successive approximation register (SAR) circuitries, and noise shaping circuitries. The capacitor arrays sample an input signal by turns, in order to provide a sampled input signal. The SAR circuitries perform an analog-to-digital conversion by turns according to a combination of the sampled input signal, a first residue signal, and a second residue signal, in order to generate digital outputs. The noise shaping circuitries receive a corresponding residue signal of the first residue signal the second residue signal in response to the analog-to-digital conversion, and to shape and transmit the corresponding residue signal to the SAR circuitries.

Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. When a first capacitor array of the capacitor arrays samples an input signal in a first phase, a second capacitor array of the capacitor arrays outputs the input signal sampled in a second phase as a sampled input signal. The SAR circuitry performs an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor that stores the residue signal generated in the second phase. The switching circuitry couples the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal.

Abstract: A switched capacitor circuit includes a first capacitor, a second capacitor, and a switching circuit. The first capacitor is configured to receive a first signal. The second capacitor is configured to receive a second signal. The switching circuit is configured to selectively couple the first capacitor and the second capacitor to an input terminal of a quantizer according to at least one clock signal. In a first configuration of the switching circuit, the first capacitor is configured to store the first signal, and the second capacitor is configured to store the second signal. In a second configuration of the switching circuit, the first capacitor and the second capacitor are stacked in series, in order to transmit a combination of the first signal and the second signal to the input terminal of the quantizer.

Abstract: This invention discloses a control circuit and a control method of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The control circuit includes a memory, an inverter and a data path. The memory is configured to store an output value of the comparator. The inverter has an output coupled to a first end of a capacitor of the switched-capacitor DAC. A second end of the capacitor is coupled to an input of the comparator. The data path, coupled between an output of the comparator and an input of the inverter, temporarily causes a voltage at the first end of the capacitor to be controlled by the output value of the comparator. The data path does not contain any memory.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) and a method of operating the SAR ADC are provided. The SAR ADC converts an analog input signal into a digital code and includes a switch-capacitor digital-to-analog converter (DAC), and the switch-capacitor DAC includes multiple capacitors. The method includes the steps of: switching terminal voltage(s) of at least one target capacitor among the capacitors according to a data in a sampling phase; sampling the analog input signal in the sampling phase; switching the terminal voltage(s) of the at least one target capacitor after the sampling phase; comparing the outputs of the switch-capacitor DAC to obtain multiple comparison results that constitute the digital code; and switching the terminal voltages of a part of the capacitors according to the comparison results.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) and a method of operating the SAR ADC are provided. The SAR ADC converts an analog input signal into a digital code and includes a switch-capacitor digital-to-analog converter (DAC), and the switch-capacitor DAC includes multiple capacitors. The method includes the steps of: switching terminal voltage(s) of at least one target capacitor among the capacitors according to a data in a sampling phase; sampling the analog input signal in the sampling phase; switching the terminal voltage(s) of the at least one target capacitor after the sampling phase; comparing the outputs of the switch-capacitor DAC to obtain multiple comparison results that constitute the digital code; and switching the terminal voltages of a part of the capacitors according to the comparison results.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes: generating a test signal for a frequency to be tested; inputting the test signal to a feedforward circuit that includes at least one adjustable impedance circuit, the test signal being inputted to the SDM through the impedance circuit; calculating an output signal of the SDM to obtain a value of a signal transfer function (STF) of the SDM at the frequency to be tested; and adjusting the impedance circuit.

Abstract: The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes: generating a test signal for a frequency to be tested; inputting the test signal to a feedforward circuit that includes at least one adjustable impedance circuit, the test signal being inputted to the SDM through the impedance circuit; calculating an output signal of the SDM to obtain a value of a signal transfer function (STF) of the SDM at the frequency to be tested; and adjusting the impedance circuit.

Abstract: The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.

Abstract: A Successive Approximation Register (SAR) Analog-to-digital converter (ADC) includes: a digital-to-analog converter (DAC), a comparison circuit and a logic circuit. The DAC is configured to generate a transformed voltage according to a digital signal and a reference voltage, and the digital signal is generated by a digital signal generating circuit. The comparison circuit is coupled to the DAC and configured to compare the transformed voltage and an input voltage to generate a comparison result, and further configured to receive a control signal. The logic circuit is coupled to the comparison circuit, and configured to perform a logic transform operation upon the comparison result to generate an output signal to the digital signal generating circuit and the comparison circuit. The control signal controls the comparison circuit to enable or disable the SAR ADC.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes the following steps: controlling the DAC not to receive the output of the quantizer; controlling the SDM to stop receiving signals; inputting a test signal to the DAC; converting the output of the loop filter to a digital signal; comparing the digital signal with a preset value; and adjusting the loop filter according to the result of comparing the digital signal and the preset value.

Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry generates a first signal according to least significant bits of an input signal, and generates a second signal according to most significant bits of the input signal. The calibration circuitry compares the first signal with the second signal to generate a calibration signal, and calibrates the DAC circuitry according to the calibration signal. The calibration signal has bits. The calibration circuitry further repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the bits, and performs a statistic operation according to the comparison results, in order to adjust the at least one bit, and a number of the at least one bit is less than a number of the bits.

Abstract: A self-test circuit and a self-test method for a comparator are provided. A first output terminal of the comparator is coupled to an input terminal of a first inverter, and a second output terminal of the comparator is coupled to an input terminal of a second inverter. The comparator operates in a reset phase or a comparison phase according to a clock. The self-test method includes steps of: coupling the first output terminal and the second output terminal so that the comparator enters a test mode; and in the test mode, controlling the comparator to operate in the reset phase or the comparison phase according to the clock. In the test mode, the first output terminal and the second output terminal have substantially the same voltage.