Patents by Inventor Shih-Hsun Hsu
Shih-Hsun Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200266231Abstract: The present disclosure relates to a semiconductor image sensor with improved quantum efficiency. The semiconductor image sensor can include a semiconductor layer having a first surface and a second surface opposite of the first surface. An interconnect structure is disposed on the first surface of the semiconductor layer, and radiation-sensing regions are formed in the semiconductor layer. The radiation-sensing regions are configured to sense radiation that enters the semiconductor layer from the second surface and groove structures are formed on the second surface of the semiconductor layer.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei CHENG, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang, Shih-Hsun Hsu
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Patent number: 10665627Abstract: A method for forming an image sensor device is provided. The method includes forming an isolation structure in a substrate. The method includes forming a light-sensing region in the substrate. The isolation structure surrounds the light-sensing region. The method includes forming a grid layer over the substrate. The grid layer is over the isolation structure and has an opening over the light-sensing region. The method includes forming a first lens in or over the opening. The method includes forming a second lens over the first lens and the grid layer.Type: GrantFiled: July 30, 2018Date of Patent: May 26, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shih-Hsun Hsu
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Patent number: 10644060Abstract: The present disclosure relates to a semiconductor image sensor with improved quantum efficiency. The semiconductor image sensor can include a semiconductor layer having a first surface and a second surface opposite of the first surface. An interconnect structure is disposed on the first surface of the semiconductor layer, and radiation-sensing regions are formed in the semiconductor layer. The radiation-sensing regions are configured to sense radiation that enters the semiconductor layer from the second surface and groove structures are formed on the second surface of the semiconductor layer.Type: GrantFiled: January 29, 2018Date of Patent: May 5, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang, Shih-Hsun Hsu
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Patent number: 10522585Abstract: A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other. The conductive layer is disposed on the first surface of the substrate. The transparent layer is disposed on the conductive layer. The transparent hard mask layer is disposed on the transparent layer, in which the substrate has an etch selectivity with respect to the transparent hard mask layer. The device layer is disposed between the carrier and the second surface of the substrate, in which various portions of the device layer are respectively exposed by various through holes which pass through the transparent hard mask layer, the transparent layer, the conductive layer, and the substrate.Type: GrantFiled: April 17, 2017Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Fang Yang, Yi-Hung Chen, Keng-Ying Liao, Yi-Jie Chen, Shih-Hsun Hsu, Chun-Chi Lee
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Publication number: 20190259800Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
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Publication number: 20190148434Abstract: A method for forming an image sensor device is provided. The method includes forming an isolation structure in a substrate. The method includes forming a light-sensing region in the substrate. The isolation structure surrounds the light-sensing region. The method includes forming a grid layer over the substrate. The grid layer is over the isolation structure and has an opening over the light-sensing region. The method includes forming a first lens in or over the opening. The method includes forming a second lens over the first lens and the grid layer.Type: ApplicationFiled: July 30, 2018Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shih-Hsun HSU
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Publication number: 20190140010Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a dielectric layer, an interconnect, a bonding pad and a dummy pattern. The semiconductor substrate has a pixel region and a circuit region. The dielectric layer is surrounded by the semiconductor substrate in the circuit region. The interconnect is disposed over the dielectric layer in the circuit region. The bonding pad is disposed in the dielectric layer and electrically connects the interconnect in the circuit region. The dummy pattern is disposed in the dielectric layer and surrounds the bonding pad in the circuit region.Type: ApplicationFiled: January 31, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
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Patent number: 10283548Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a dielectric layer, an interconnect, a bonding pad and a dummy pattern. The semiconductor substrate has a pixel region and a circuit region. The dielectric layer is surrounded by the semiconductor substrate in the circuit region. The interconnect is disposed over the dielectric layer in the circuit region. The bonding pad is disposed in the dielectric layer and electrically connects the interconnect in the circuit region. The dummy pattern is disposed in the dielectric layer and surrounds the bonding pad in the circuit region.Type: GrantFiled: January 31, 2018Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
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Publication number: 20190096951Abstract: The present disclosure relates to a semiconductor image sensor with improved quantum efficiency. The semiconductor image sensor can include a semiconductor layer having a first surface and a second surface opposite of the first surface. An interconnect structure is disposed on the first surface of the semiconductor layer, and radiation-sensing regions are formed in the semiconductor layer. The radiation-sensing regions are configured to sense radiation that enters the semiconductor layer from the second surface and groove structures are formed on the second surface of the semiconductor layer.Type: ApplicationFiled: January 29, 2018Publication date: March 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., LTD.Inventors: YUN-WEI CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Hsun-Ying HUANG, Shih-Hsun HSU
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Publication number: 20180301501Abstract: A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other. The conductive layer is disposed on the first surface of the substrate. The transparent layer is disposed on the conductive layer. The transparent hard mask layer is disposed on the transparent layer, in which the substrate has an etch selectivity with respect to the transparent hard mask layer. The device layer is disposed between the carrier and the second surface of the substrate, in which various portions of the device layer are respectively exposed by various through holes which pass through the transparent hard mask layer, the transparent layer, the conductive layer, and the substrate.Type: ApplicationFiled: April 17, 2017Publication date: October 18, 2018Inventors: Yi-Fang Yang, Yi-Hung Chen, Keng-Ying Liao, Yi-Jie Chen, Shih-Hsun Hsu, Chun-Chi Lee
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Patent number: 9601443Abstract: A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.Type: GrantFiled: February 13, 2007Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Shih-Hsun Hsu, Shih-Cheng Chang, Shang-Yun Hou, Hsien-Wei Chen, Chia-Lun Tsai, Benson Liu, Shin-Puu Jeng, Anbiarshy Wu
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Patent number: 8993355Abstract: A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.Type: GrantFiled: July 30, 2013Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Chia-Lun Tsai, Shang-Yun Hou, Shin-Puu Jeng, Shih-Hsun Hsu, Wei-Ti Hsu, Lin-Ko Feng, Chun-Jen Chen
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Patent number: 8772137Abstract: A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed.Type: GrantFiled: December 18, 2013Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Wei Chen, Shih-Hsun Hsu
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Patent number: 8749020Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line.Type: GrantFiled: March 9, 2007Date of Patent: June 10, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Shin-Puu Jeng, Shih-Hsun Hsu
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Publication number: 20140106544Abstract: A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Wei CHEN, Shih-Hsun HSU
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Patent number: 8643147Abstract: An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line.Type: GrantFiled: November 1, 2007Date of Patent: February 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu Jeng, Shih-Hsun Hsu, Shang-Yun Hou, Hao-Yi Tsai, Chen-Hua Yu
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Patent number: 8629532Abstract: A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed.Type: GrantFiled: May 8, 2007Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsien-Wei Chen, Shih-Hsun Hsu
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Publication number: 20130316471Abstract: A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.Type: ApplicationFiled: July 30, 2013Publication date: November 28, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Chia-Lun Tsai, Shang-Yun Hou, Shin-Puu Jeng, Shih-Hsun Hsu, Wei-Ti Hsu, Lin-Ko Feng, Chun-Jen Chen
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Patent number: 8519512Abstract: A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.Type: GrantFiled: September 22, 2006Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Chia-Lun Tsai, Shang-Yun Hou, Shin-Puu Jeng, Shih-Hsun Hsu, Wei-Ti Hsu, Lin-Ko Feng, Chun-Jen Chen
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Patent number: 8227917Abstract: A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such that adjacent bonding pads have their bond ball on opposite sides in relation to the adjacent bonding pad.Type: GrantFiled: October 8, 2007Date of Patent: July 24, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Hsun Hsu, Hao-Yi Tsai, Benson Liu, Chia-Lun Tsai, Hsien-Wei Chen, Anbiarshy N. F. Wu, Shang-Yun Hou, Shin-Puu Jeng