Abstract: An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.

Abstract: An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circuit structure further includes a first passivation layer over a top dielectric layer; and a trench extending from a top surface of the first passivation layer into the first passivation layer, wherein the trench substantially forms a ring. Each side of the ring is adjacent to a respective edge of the semiconductor chip. At least one of the plurality of vias has a width greater than about 70 percent of a width of a respective overlying metal line in the plurality of metal lines.

Abstract: Bonding pad structures and integrated circuits having the same are provided. An exemplary embodiment of a bond pad structure comprises a bond pad layer. A passivation layer partially covers the bond pad layer from edges thereof and exposes a bonding surface, wherein the passivation layer is formed with a recess on at least one edge of the bonding surface to thereby define a probe needle contact area for probe needle testing and a wire bonding area for wire bonding on the bonding surface, and the probe needle contact area and the wire bonding area have a non-overlapping relationship.

Abstract: A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads and power bond pads formed on the IC chip. The contact pads are coupled to the associated bond pads by a bonding wire. The bonding wires that connect the power and ground pads have a thickness that is greater than the thickness of the bonding wires that couple the signal pads. The various bond pads on the IC chip may be staggered to provide for enhanced compactness and integration. The package substrates may be a plurality of stacked package substrates.

Abstract: A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.

Abstract: An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.

Abstract: An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different from the pad density of the pad structure of the first interconnect layer. The pad structures of the first and second interconnect layers are connected to each other.

Abstract: Reinforced semiconductor structures are provided. An exemplary embodiment of a reinforced semiconductor structure comprises a semiconductor wafer comprising a plurality of dielectric layers formed thereon. At least one scribe line region is defined over the semiconductor wafer, separating the semiconductor wafer with at least two active regions thereover. A plurality of first non-dielectric pillars are formed in the topmost layer of the dielectric layers in the scribe line region and surround the test pad along a periphery. A plurality of second non-dielectric pillars and first vias are formed in a first low-k dielectric layer underlying the topmost low-k layer in the scribe line region, wherein the second non-dielectric pillars electrically connect the first non-dielectric pillars by the first vias, respectively.

Abstract: An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.

Abstract: A novel die saw crack stopper that consists of placing formations into the scribe line of multiple metal layers of a die. These formations comprise multiple right angle shapes that are interconnected at right angles. In an embodiment the formations have an overall shape that has a special meaning, such as a single right angle “z” shape along with a discontinuous cross piece, two interlocking right angle “z” shapes, “t”, multiple sets of parallel lines perpendicular to each other, with one set having a line that only intersects a single line from the other set, or the like. The formations in a single layer can be placed such that they are located adjacent to each other along an axis that runs substantially parallel with the scribe line. These formations can also be connected to other formations in other metal layers located either above or below the formation.

Abstract: A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.

Abstract: A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.

Abstract: An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line.

Abstract: A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such that adjacent bonding pads have their bond ball on opposite sides in relation to the adjacent bonding pad.

Abstract: A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads and power bond pads formed on the IC chip. The contact pads are coupled to the associated bond pads by a bonding wire. The bonding wires that connect the power and ground pads have a thickness that is greater than the thickness of the bonding wires that couple the signal pads. The various bond pads on the IC chip may be staggered to provide for enhanced compactness and integration. The package substrates may be a plurality of stacked package substrates.

Abstract: An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.

Abstract: A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.

Abstract: An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circuit structure further includes a first passivation layer over a top dielectric layer; and a trench extending from a top surface of the first passivation layer into the first passivation layer, wherein the trench substantially forms a ring. Each side of the ring is adjacent to a respective edge of the semiconductor chip. At least one of the plurality of vias has a width greater than about 70 percent of a width of a respective overlying metal line in the plurality of metal lines.

Abstract: A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed.

Abstract: A test structure for use in a semiconductor chip. In a preferred embodiment, a number of die are formed in an array on a semiconductor wafer substrate. Each die includes an active area defined by a seal ring and is separated from those adjacent to it by a thin scribe line. In addition to the operational structures formed in the active area of each die, one or more test structures are formed. In a preferred embodiment, these test structures are formed into one or more PCM (process control monitor) test pattern layout areas that are positioned near the seal ring and outside of the operational bond pads. Some or all of individual pads in the PCM test pattern layout area may then be connected to corresponding features on adjacent dice, and in some applications enable the simultaneous performance of WAT (wafer acceptance test) and CP (circuit probe) testing.