Abstract: A multilayer structure includes a substrate and a plurality of sub-stacks extending along a first direction respectively and disposed on an upper surface of the substrate along a second direction. Each of the sub-stacks includes insulating layers and patterned sacrificial layers alternately stacked on the upper surface along a third direction; conductive layers alternately stacked on the upper surface with the insulating layers along the third direction; and interlayer connectors extending along the third direction; wherein the patterned sacrificial layers have first sides and second sides opposite to the first sides, the conductive layers include first side conductive layers corresponding to the first sides and second side conductive layers corresponding to the second sides; wherein the interlayer connectors are electrically connected and directly contact corresponding ones of the conductive layers, and the first direction, the second direction, and the third direction are crossed.

Abstract: A neuromorphic computing device includes synapse weights. The synapse weights have different weight values resulted from different transistor arrangements of the synapse weights.

Abstract: A neuromorphic computing device includes first neural circuits, second neural circuits and synapse weights. The first neural circuits are disposed in a first neural region. The second neural circuits are disposed in a second neural region. The synapse weights are electrically connected between the first neural circuits and the second neural circuits, and disposed in a synapse region. The first neural region and the second neural region are on opposing sides of the synapse region respectively.

Abstract: A resistor circuit, an artificial intelligence chip and a method for manufacturing the same are provided. The resistor circuit includes a stack structure. The stack structure includes resistive material layers and insulating layers stacked alternately. The resistor circuit includes at least two unit resistors electrically connected in series or parallel. The at least two unit resistors are respectively defined in the resistive material layers of different layers.

Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

Abstract: A semiconductor device and a method for forming such are provided, the device including: a substrate, a plurality of parallel active semiconductor patterns that extend through a drain-side region and a source-side region, a metal drain contact in the drain-side region, an active gate pattern, a first dummy gate pattern, and a second dummy gate pattern that all extend across the active semiconductor patterns, and a metal interconnect structure located in a region between the first and the second dummy gate patterns. The active semiconductor patterns are doped with a dopant in portions exposed by the dummy gates in dummy gate regions that include the gate cut regions of the first and second dummy gate patterns. The metal interconnect structure connects each of a second subset of the active semiconductor patterns to a respective at least one of a first subset of the active semiconductor patterns.

Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.

Abstract: A detection system and associated detection method for detecting an arcing phenomenon in a chamber are provided. In the chamber, a plurality of semiconductor chips are manufactured on at least one wafer. The detection system includes at least one optical sensor and a control circuit. Being configured for detecting the intensity of the light signal in the chamber, the at least one optical sensor is placed in the chamber. Accordingly, the optical sensor generates a plurality of intensity detected results, wherein the light signal continuously lasts in the chamber while the plurality of semiconductor chips are manufactured. The control circuit is in communication with the optical sensor. Then, the control circuit identifies whether the arcing phenomenon occurred according to the plurality of intensity detected results.

Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

Abstract: A semiconductor device for electric discharge protection is disclosed. In one aspect, the semiconductor device includes a substrate having a p-type doping. The semiconductor device includes a first well and a second well having an n-type doping and arranged spaced apart within a surface layer of the substrate, and a third well having a p-type doping and arranged in the surface layer of the substrate between the first well and the second well. The semiconductor device further includes an emitter region and a base contact region having a p-type doping and arranged within a surface layer of the first well, and a collector region having a p-type doping. The collector region is arranged at least partly within a surface layer of the third well and such that it overlaps both of the first well and the second well. An integrated circuit including a semiconductor device is also provided.

Abstract: A semiconductor device for electric discharge protection is disclosed. In one aspect, the semiconductor device includes a substrate having a p-type doping. The semiconductor device includes a first well and a second well having an n-type doping and arranged spaced apart within a surface layer of the substrate, and a third well having a p-type doping and arranged in the surface layer of the substrate between the first well and the second well. The semiconductor device further includes an emitter region and a base contact region having a p-type doping and arranged within a surface layer of the first well, and a collector region having a p-type doping. The collector region is arranged at least partly within a surface layer of the third well and such that it overlaps both of the first well and the second well. An integrated circuit including a semiconductor device is also provided.

Abstract: A 3D stacking semiconductor device and a manufacturing method thereof are provided. The method includes using a set of N etch masks for creating O different numbers of removed layers in the conductive layers and the insulating layers for forming landing areas on the conductive layers in the contact region, each mask including mask and etch regions, N being an integer equal to or larger than 2, O being an integer larger than 2, 2N-1<O?2N; and removing a portion of the conductive layers and the insulating layers to create etched depths extending from a surface layer to the corresponding landing areas on the conductive layers; wherein the etched depths of corresponding etching steps are 1P, 2P and nP layers of the stacking structures, n being an integer equal to or larger than 3, and P being an integer equal to or larger than 1.

Abstract: A method for manufacturing a multi-layer structure is provided. The method includes following steps. First, a stack of alternate conductive layers and insulating layers is formed on a substrate, and the stack includes a multi-layer area and a contact area adjacent to the multi-layer area. Next, a plurality of first openings are formed in the contact area. Then, a conductive connecting structure is formed on the stack and into the first openings. Thereafter, the stack is patterned. The conductive connecting structure continuously extends on the contact area and into the first openings to maintain an electrical connection among the conductive layers while the stack is patterned.

Abstract: A memory structure is provided. The memory structure comprises M array regions and N contact regions. M is an integer ?2. N is an integer ?M. Each array region is coupled to at least one contact region. Each contact region comprises a stair structure and a plurality of contacts. The stair structure comprises alternately stacked conductive layers and insulating layers. Each contact is connected to one conductive layer of the stair structure. Two array regions which are adjacent to each other are spatially separated by two contact regions, which are coupled to the two array regions, respectively.

Abstract: A 3D stacking semiconductor device and a manufacturing method thereof are provided. The method includes using a set of N etch masks for creating O different numbers of removed layers in the conductive layers and the insulating layers for forming landing areas on the conductive layers in the contact region, each mask including mask and etch regions, N being an integer equal to or larger than 2, O being an integer larger than 2, 2N-1<O?2N; and removing a portion of the conductive layers and the insulating layers to create etched depths extending from a surface layer to the corresponding landing areas on the conductive layers; wherein the etched depths of corresponding etching steps are 1P, 2P and nP layers of the stacking structures, n being an integer equal to or larger than 3, and P being an integer equal to or larger than 1.

Abstract: A 3D semiconductor device is provided, including several memory layers vertically stacked on a substrate, an upper selection layer formed on the memory layers, a lower selection layer formed above the substrate, several strings formed vertically to the memory layers and the substrate, several bit lines parallel to each other and disposed above the substrate. The memory layers are parallel to each other, and the strings are electrically connected to the upper selection layer and the lower selection layer. The bit lines are positioned under the memory layers.

Abstract: A bumpless fan-out chip stacking structure includes a first die disposed on the substrate, a first dielectric layer conformally covering on the first die, a first RDL disposed on the first dielectric layer, a first via plug electrically connecting the first die to the first RDL, a first capping layer conformally covering on the first RDL, a second die attached on the first capping layer, a second dielectric layer conformally covering on the second die, a second RDL disposed on the second dielectric layer, a second via plug electrically connecting the second die to the second RDL, a second capping layer conformally covering on the second RDL, a patterned conductive layer disposed on the second capping layer and an interlayer connection structure electrically connecting the patterned conductive layer to the first RDL and the second RDL respectively.

Abstract: A memory device is disclosed. The memory device includes a memory array. The memory array includes a main memory block and an extra memory block. The memory array includes a main bit line and an extra bit line. A ratio of a quantity of the extra memory block to a quantity of the main memory block is a block quantity ratio A. A ratio of a quantity of the extra bit line to a quantity of the main bit line is a bit line quantity ratio B. The block quantity ratio A is larger than the bit line quantity ratio B.