Abstract: Embodiments of mechanisms for processing a wafer are provided. A method for processing a wafer includes creating an exhaust flow in a fluid conduit assembly that is connected to a process module used for processing the wafer. The method also includes detecting the exhaust pressure in the fluid conduit assembly. The method further includes determining whether the exhaust pressure meets a set point. In addition, the method includes regulating the exhaust flow if the exhaust pressure fails to meet the set point.

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a ground layer disposed on the substrate, a stacking structure having a plurality of conductive layers and a plurality of insulating layers alternatively stacked on the ground layer and a plurality of memory strings penetrating through the stacking structure. The ground layer includes a metal layer. The memory strings electrically contact with the metal layer.

Abstract: A connector structure for electrically contacting with a conductive layer disposed on a substrate is provided. The connector structure comprises a conductive connecting element disposed on the substrate. The conductive connecting element comprises a connecting part and an extending part. The connecting part has a bottom portion electrically contacting with the conductive layer. The extending part laterally extends outwards from a top portion of the connecting part, and the extending part and the connecting part are respectively formed of different materials.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure comprises a substrate, a first chip, a first dielectric layer, a dielectric encapsulation layer and at least one first via. The first chip is disposed on the substrate. The first chip has a first landing area. The first dielectric layer is disposed on the first chip. The dielectric encapsulation layer encapsulates the first chip and the first dielectric layer. The at least one first via penetrates through the dielectric encapsulation layer and the first dielectric layer. The at least one first via connects to the first landing area of the first chip.

Abstract: A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer ?2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=? to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines.

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into separate word lines, each defining a block of memory cells. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. String select lines run above the conductive layers, each intersection of a pillar and an string select line defining a respective select gate of the pillar. Bit lines run above the SSLs. Ground select lines run below the conductive layers, each intersection of a pillar and a ground select line defining a respective ground select gate of the pillar. The ground select lines are divided laterally such that the number of ground select lines in each block is greater than 1 but less than the number of string select lines in the block.

Abstract: A memory structure is provided. The memory structure includes a substrate, an array portion disposed on the substrate, a periphery portion disposed on the array portion, and a plurality of contacts connecting the array portion to the periphery portion.

Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, a top plane of conductive strips, and an additional intermediate plane. A plurality of vertical structures is arranged orthogonally to the plurality of stacks. Memory elements are disposed in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of vertical structures. A stack of linking elements is connected to conductive strips in respective intermediate planes and to the additional intermediate plane. Decoding circuitry is coupled to the plurality of intermediate planes and the additional intermediate plane, and is configured to replace an intermediate plane indicated to be defective with the additional intermediate plane.

Abstract: Embodiments of mechanisms for measuring the distance between a robot blade and at least one measurement target are provided. A method for measuring the distance includes emitting a signal to the measurement target by a signal source assembly. The method also includes receiving the signal reflected from the measurement target by a signal reception assembly. The method further includes determining the distance between the robot blade and the measurement target. The distance is determined based on the time difference between the emission of the signal from the signal source assembly and the receipt of the signal by the signal reception assembly.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure comprises a substrate, a first chip, a first dielectric layer, a dielectric encapsulation layer and at least one first via. The first chip is disposed on the substrate. The first chip has a first landing area. The first dielectric layer is disposed on the first chip. The dielectric encapsulation layer encapsulates the first chip and the first dielectric layer. The at least one first via penetrates through the dielectric encapsulation layer and the first dielectric layer. The at least one first via connects to the first landing area of the first chip.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first stacked structure. The first stacked structure includes a first stacked portion disposed along a first direction, at least one second stacked portion connected with the first stacked portion and disposed along a second direction perpendicular to the first direction, and at least one third stacked portion connected with the first direction and arranged alternately with the second stacked portion along the first direction. The width of the third stacked portion is smaller than the width of the second stacked portion along the second direction.

Abstract: A three-dimensional (3D) semiconductor device is provided, comprising a substrate having a staircase region comprising N steps, wherein N is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising a plurality of sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps to form respective contact regions; and a plurality of connectors formed in the respective contact regions, and the connectors extending downwardly to connect a bottom layer under the multi-layers.

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. SSLs run above the conductive layers, each intersection of a pillar and an SSL defining a respective select gate of the pillar. Bit lines run above the SSLs. The pillars are arranged on a regular grid which is rotated relative to the bit lines. The grid may have a square, rectangle or diamond-shaped unit cell, and may be rotated relative to the bit lines by an angle ? where tan(?)=±X/Y, where X and Y are co-prime integers. The SSLs may be made wide enough so as to intersect two pillars on one side of the unit cell, or all pillars of the cell, or sufficiently wide as to intersect pillars in two or more non-adjacent cells.

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into separate word lines, each defining a block of memory cells. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. String select lines run above the conductive layers, each intersection of a pillar and an string select line defining a respective select gate of the pillar. Bit lines run above the SSLs. Ground select lines run below the conductive layers, each intersection of a pillar and a ground select line defining a respective ground select gate of the pillar. The ground select lines are divided laterally such that the number of ground select lines in each block is greater than 1 but less than the number of string select lines in the block.

Abstract: A memory repairing method and a memory device applying the same are disclosed, wherein the method comprises steps as follows: A memory device comprising at least one page having a plurality of cell strings is firstly provided. A regular data pattern is then provided to block at least two of the plurality of cell strings, and the blocked cells strings are marked as inaccessible.

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into word lines. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the layers. String select lines run above the conductive layers and define select gates of the pillars. Bit lines run above the SSLs. The pillars are arranged on a regular grid having a unit cell area ?, and adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (?/pBL). Ground select lines run below the conductive layers and define ground select gates of the pillars. The ground select lines, too, may have respective widths in the bit line direction which are at least as large as (?/pBL).

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.

Abstract: A memory device comprises plural of silicon-containing layers, string select lines (SSLs), strings, bit lines, metal strapped word lines and plural sets of multi-plugs structure. The silicon-containing layers stacked at a substrate. The SSLs are disposed on the silicon-containing layers and extend along a first direction. The strings are perpendicular to the silicon-containing layers and the SSLs and electrically connected to the SSLs. The bit lines are disposed on the SSLs extending along a second direction and electrically connected to the strings. The plural sets of multi-plugs structure are arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure, wherein each set of multi-plugs structure has plural plugs each corresponding to and connected with one of the silicon-containing layers. Each of the metal strapped word lines is connected to the plugs that are connected to the identical silicon-containing layer.

Abstract: A memory device includes a plurality of stacks of conductive strips, a plurality of conductive vertical structures arranged orthogonally to the plurality of stacks, memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of conductive vertical structures, multiples pluralities of conductive lines, and control circuitry. The plurality of stacks of conductive strips alternate with insulating strips, including at least a bottom layer of conductive strips, a plurality of intermediate layers of conductive strips, and a top layer of conductive strips. A first plurality of conductive lines electrically couple to the top layer of the conductive strips. A second plurality of conductive lines and a third plurality of conductive lines electrically couple to the plurality of intermediate layers.

Abstract: A memory device includes a plurality of stacks of conductive strips, a plurality of conductive vertical structures arranged orthogonally to the plurality of stacks, memory elements in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of conductive vertical structures, multiples pluralities of conductive lines, and control circuitry. The plurality of stacks of conductive strips alternate with insulating strips, including at least a bottom layer of conductive strips, a plurality of intermediate layers of conductive strips, and a top layer of conductive strips. A first plurality of conductive lines electrically couple to the top layer of the conductive strips. A second plurality of conductive lines and a third plurality of conductive lines electrically couple to the plurality of intermediate layers.