Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The first gate stack includes a first gate and a second gate over the first gate, and the first gate and the second gate are electrically isolated from each other. The semiconductor device structure includes a ring structure surrounding the first gate stack. The ring structure is made of a conductive material.

Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.

Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.

Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The first gate stack includes a first gate and a second gate over the first gate, and the first gate and the second gate are electrically isolated from each other. The semiconductor device structure includes a ring structure surrounding the first gate stack. The ring structure is made of a conductive material.

Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A fist inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.

Abstract: A loop antenna is provided, which includes a first loop section, a second loop section and a third loop section. The first loop section surrounds and defines an empty area. The second loop section surrounds and connects the first loop section, and an annular groove is formed between the first loop section and the second loop section. The third loop section surrounds and connects the second loop section. The width of a gap between the third loop section and the second loop section is smaller than the width of the annular groove.

Abstract: A transmission device for a near field communication (NFC) device includes a matching circuit, a connecting interface with a first width for connecting an operating circuit of the NFC device, a first transmission line electrically connected between an antenna of the NFC device and the matching circuit, and a second transmission line electrically connected between connecting interface and the matching circuit, including an increasing width portion and a constant width portion, wherein a width of the second transmission increases from the first width to a second width within the increasing width portion and keeps the second width within the constant width portion, wherein the second width is greater than and related to the first width.

Abstract: A loop antenna is provided, which includes a first loop section, a second loop section and a third loop section. The first loop section surrounds and defines an empty area. The second loop section surrounds and connects the first loop section, and an annular groove is formed between the first loop section and the second loop section. The third loop section surrounds and connects the second loop section. The width of a gap between the third loop section and the second loop section is smaller than the width of the annular groove.

Abstract: A transmission device for a near field communication (NFC) device includes a matching circuit, a connecting interface with a first width for connecting an operating circuit of the NFC device, a first transmission line electrically connected between an antenna of the NFC device and the matching circuit, and a second transmission line electrically connected between connecting interface and the matching circuit, including an increasing width portion and a constant width portion, wherein a width of the second transmission increases from the first width to a second width within the increasing width portion and keeps the second width within the constant width portion, wherein the second width is greater than and related to the first width.

Abstract: A modified sodium iodide symporter (NIS) protein is provided. The modified NIS protein comprises an amino acid sequence of SEQ ID NO.1 with the proviso that at least one amino acid residue within SEQ ID NO. 1 is changed. The modified NIS protein has an enhanced transport function, and the expression of the modified NIS protein in the cells results in higher intracellular levels of a substrate of a NIS protein than does the expression of the same amount of a wild-type NIS protein.

Abstract: A gain control circuit of the wireless receiver comprises a plurality of stages-amplifier, an analog gain control circuit, and a digital gain control circuit, wherein the analog gain control circuit generates an analog controlling voltage for regulating the gain of the post-amplifier by an analog gain controlling process, and the digital gain control circuit is used for determining a plurality of gain curves for the pre-amplifier, and the gain curves are all operating between the first default voltage and second default voltage. While the analog controlling voltage is over the first default voltage or second default voltage, the gain curve will be switched, thereby, the analog gain controlling process can be with the digital gain controlling process therein for improving the linearity of the gain regulation and reducing the transient response during the gain switching process.

Abstract: A modified sodium iodide symporter (NIS) protein is provided. The modified NIS protein comprises an amino acid sequence of SEQ ID NO.1 with the proviso that at least one amino acid residue within SEQ ID NO. 1 is changed. The modified NIS protein has an enhanced transport function, and the expression of the modified NIS protein in the cells results in higher intracellular levels of a substrate of a NIS protein than does the expression of the same amount of a wild-type NIS protein.

Abstract: A gain control circuit of the wireless receiver comprises a plurality of stages-amplifier, an analog gain control circuit, and a digital gain control circuit, wherein the analog gain control circuit generates an analog controlling voltage for regulating the gain of the post-amplifier by an analog gain controlling process, and the digital gain control circuit is used for determining a plurality of gain curves for the pre-amplifier, and the gain curves are all operating between the first default voltage and second default voltage. While the analog controlling voltage is over the first default voltage or second default voltage, the gain curve will be switched, thereby, the analog gain controlling process can be with the digital gain controlling process therein for improving the linearity of the gain regulation and reducing the transient response during the gain switching process.

Abstract: A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interpolation points. The interpolation point VCOs are pre-calibrated with a predetermined voltage and the resultingly generated frequency for each of the interpolation point VCOs is stored into memory as a (frequency, VCO) pair, one pair for each interpolation point VCO. When a desired frequency then is given to the system, an appropriate VCO is selected by interpolation using the (frequency, VCO) pairs of the two most adjacent interpolation points for tracking and locking.

Abstract: An optical compensation structure and its fabricating process are disclosed. The optical compensation structure comprises an upper polarizer film, a transparent substrate, a first retarder film (C+ plate), and a second retarder film (A-plate). The upper polarizer film provides polarization function and possesses a top surface and a bottom surface. The transparent substrate is directly laminated onto the top surface of upper polarizer film. The first retarder film is coated with a bonding layer made of crosslinking agent on one side and the bonding layer is directly laminated onto the bottom surface of upper polarizer film. The second retarder film binds to the side of first retarder film away from the upper polarizer film.

Abstract: The present invention discloses a capsular endoscope device with an orientation/release mechanism. The capsular endoscope device of the present invention has a casing with the front end thereof having a hose, and the front end of the hose has a capsular-endoscope control device, which a capsular endoscope can be attached to. A deflection control device, which is installed to the casing, is used to deflect the capsular-endoscope control device so that the capsular endoscope will be moved to have an elevation angle. A rotation/release control device, which is installed inside the casing, is used to rotate the capsular-endoscope control device so that the capsular endoscope will be rotated also. The rotation/release control device can also release the capsular endoscope from the capsular-endoscope control device.