Patents by Inventor Shih Pei Chou

Shih Pei Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180226449
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 9, 2018
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10038026
    Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3DIC includes a first substrate including a photodetector which is configured to receive light in a first direction from a light source. An interconnect structure is disposed over the first substrate, and includes a plurality of metal layers and insulating layers that are over stacked over one another in alternating fashion. One of the plurality of metal layers is closest to the light source and another of the plurality of metal layers is furthest from the light source. A bond pad recess extends into the interconnect structure from an opening in a surface of the 3DIC which is nearest the light source and terminates at a bond pad. The bond pad is spaced apart from the surface of the 3DIC and is in direct contact with the one of the plurality of metal layers that is furthest from the light source.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sin-Yao Huang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang, Shih Pei Chou
  • Patent number: 10008531
    Abstract: An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first region, and a second isolation trench is formed in the second region. A first liner layer is formed in the first isolation trench, and a second liner layer is formed in the second isolation trench. The second liner layer has a physical characteristic that is different from a corresponding physical characteristic of the first liner layer. An implantation procedure is performed on the second isolation trench and the second liner layer formed therein. The physical characteristic of the second liner layer may be selected to enhance an implantation depth or an implantation uniformity compared to the first liner layer.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: June 26, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Chou, Chia-Shiung Tsai, Feng-Chi Hung, Jiech-Fun Lu, Min-Feng Kao, Shih Pei Chou, Yeur-Luen Tu
  • Patent number: 9991303
    Abstract: An image sensor structure is provided. The image sensor device structure includes a substrate, and the substrate includes an array region and a peripheral region. The image sensor device structure includes an anti-reflection layer formed on the substrate and a buffer layer formed on the anti-reflection layer. The image sensor device structure includes a first etch stop layer formed on the buffer layer and a metal grid structure formed on the first etch stop layer. The image sensor device structure also includes a dielectric layer formed on the metal grid structure.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Wen Hsu, Ching-Chung Su, Cheng-Hsien Chou, Jiech-Fun Lu, Shih-Pei Chou, Yeur-Luen Tu
  • Patent number: 9941320
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20180068965
    Abstract: A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.
    Type: Application
    Filed: November 1, 2017
    Publication date: March 8, 2018
    Inventors: Sheng-Chau Chen, Shih Pei Chou, Yen-Chang Chu, Cheng-Hsien Chou, Chih-Hui Huang, Yeur-Luen Tu
  • Patent number: 9887182
    Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ju-Shi Chen, Cheng-Ying Ho, Chun-Chieh Chuang, Sheng-Chau Chen, Shih Pei Chou, Hui-Wen Shen, Dun-Nian Yaung, Ching-Chun Wang, Feng-Chi Hung, Shyh-Fann Ting
  • Publication number: 20180033749
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Inventors: Sheng-Chau CHEN, Shih-Pei CHOU, Ming-Che LEE, Kuo-Ming WU, Cheng-Hsien CHOU, Cheng-Yuan TSAI, Yuer-Luen TU
  • Publication number: 20180012870
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
    Type: Application
    Filed: September 5, 2017
    Publication date: January 11, 2018
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, U-Ting Chen, Shih Pei Chou
  • Publication number: 20170373117
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Application
    Filed: August 28, 2017
    Publication date: December 28, 2017
    Inventors: Cheng-Hsien Chou, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Hsiao-Hui Tseng, Min-Ying Tsai
  • Patent number: 9842816
    Abstract: A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Shih Pei Chou, Yen-Chang Chu, Cheng-Hsien Chou, Chih-Hui Huang, Yeur-Luen Tu
  • Publication number: 20170309603
    Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges.
    Type: Application
    Filed: May 17, 2017
    Publication date: October 26, 2017
    Inventors: Ju-Shi Chen, Cheng-Ying Ho, Chun-Chieh Chuang, Sheng-Chau Chen, Shih Pei Chou, Hui-Wen Shen, Dun-Nian Yaung, Ching-Chun Wang, Feng-Chi Hung, Shyh-Fann Ting
  • Publication number: 20170301611
    Abstract: The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Inventors: YU-HUNG CHENG, SHIH-PEI CHOU, YEUR-LUEN TU, ALEXANDER KALNITSKY, TUNG-I LIN, WEI-LI CHEN
  • Publication number: 20170301709
    Abstract: The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Chih-Hui Huang, Shyh-Fann Ting, Shih Pei Chou, Sheng-Chan Li
  • Patent number: 9786619
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Shih-Pei Chou, Ming-Jhe Lee, Kuo-Ming Wu, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yeur-Luen Tu
  • Patent number: 9754925
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, U-Ting Chen, Shih-Pei Chou
  • Patent number: 9754993
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Hsiao-Hui Tseng, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Min-Ying Tsai
  • Publication number: 20170243915
    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.
    Type: Application
    Filed: May 10, 2017
    Publication date: August 24, 2017
    Inventors: Cheng-Hsien Chou, Shih Pei Chou, Chih-Yu Lai, Sheng-Chau Chen, Chih-Ta Chen, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 9728570
    Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Chih-Hui Huang, Shyh-Fann Ting, Shih Pei Chou, Sheng-Chan Li
  • Publication number: 20170207176
    Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai, Wei-Cheng Hsu, Hsiao-Hui Tseng, Shih Pei Chou, Shyh-Fann Ting, Tzu-Hsuan Hsu, Ching-Chun Wang, Yeur-Luen Tu, Dun-Nian Yaung