Patents by Inventor Shih-Ping Hsu

Shih-Ping Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031329
    Abstract: A method of fabricating a packaging substrate is provided, which includes: forming on a carrier a conductor layer having a plurality of openings; forming a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body disposed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with the conductive pad and less in width than the conductive pad; forming a plurality of conductive posts on the conductive pads; forming on the carrier a first insulating layer that encapsulates the conductive bumps and the conductive posts; removing the carrier; and removing the entire conductor layer to expose the post bodies from a first surface of the first insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 8, 2021
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chu-Chin Hu, Shih-Ping Hsu, Che-Wei Hsu, Chin-Ming Liu, Chih-Kuai Yang
  • Publication number: 20210098351
    Abstract: A flip-chip package substrate and a method for fabricating the same are provided. An insulation layer is formed on two opposing sides of a middle layer to form a composite core structure and increase the rigidity of the flip-chip package substrate. Therefore, the core structure can be made thinner. The conductive structures can also have a smaller end size, and more conductive points can be disposed within a unit area. Therefore, a circuit structure can be produced that have a fine line pitch and a high wiring density, satisfy the packaging demands of highly integrated circuit/large size substrate, and avoid an electronic package from being warpage.
    Type: Application
    Filed: September 15, 2020
    Publication date: April 1, 2021
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Patent number: 10896882
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes bonding a portion of an inactive surface of an electronic component to a thermal conductive layer of a heat dissipating element, encapsulating the electronic component and the thermal conductive layer with an encapsulant, and forming a circuit structure on the encapsulant and electrically connecting the circuit structure to the electronic component. Since the heat dissipating element is bonded to the electronic component through the thermal conductive layer, the heat dissipating effect of the electronic package is improved.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 19, 2021
    Assignee: PHOENIX & CORPORATION
    Inventors: Shih-Ping Hsu, Che-Wei Hsu, Chih-Kuai Yang
  • Publication number: 20200388552
    Abstract: A semiconductor package carrier board, a method for fabricating the same, and an electronic package having the same are provided. The method includes forming on a circuit structure a graphene layer that acts as an insulation heat dissipating layer. Since the heat conductivity of the graphene layer is far greater than the heat conductivity of ink (about 0.4 W/m·k), which is used as solder resist, the heat of the semiconductor package carrier board can be conducted quickly, and thus can avoid the problem that the heat will be accumulated on the semiconductor package carrier board.
    Type: Application
    Filed: June 5, 2020
    Publication date: December 10, 2020
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Wen-Chang Chen
  • Publication number: 20200388564
    Abstract: A semiconductor package substrate, a method for fabricating the same, and an electronic package having the same are provided. The method includes: providing a circuit structure having a first solder pad and a second solder pad; forming on the circuit structure a metal sheet having a first hole, from which the first solder pad is exposed, and a second hole, from which the second solder pad is exposed; and forming an insulation layer on the metal sheet and a hole wall of the second hole. A first conductive element that is to be grounded is disposed in the first hole and is in contact with the metal sheet and the first solder pad. Therefore, heat generated in a signal transmission process is dissipated by the metal sheet and the first conductive element.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 10, 2020
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Publication number: 20200332429
    Abstract: This disclosure provides a package substrate fabrication method including: providing a carrier; forming a first dielectric layer on the carrier while enabling the first dielectric layer to be patterned including an opening; forming a first conducting unit on the carrier while enabling the first conducting unit to fill up the opening, a height of the first conducting unit at the opening larger than a thickness of the first dielectric layer, and a width of the first conducting unit larger than a width of the opening; forming a second dielectric layer on the first conducting unit; forming a second conducting unit on the second dielectric layer; forming a third dielectric layer on the second conducting unit; removing the carrier and the first dielectric layer while enabling the part of the first conducting unit in the opening to be removed; and forming a fourth dielectric layer to cover the first conducting unit.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Inventors: CHUN-HSIEN YU, SHIH-PING HSU, PAO-HUNG CHOU
  • Publication number: 20200312756
    Abstract: A semiconductor packaging substrate and a method for fabricating the same are provided. The method includes forming a solder resist structure having a hole on a circuit structure, with a portion of the circuit structure exposed from the hole, and forming a cup-shaped solder stand on the exposed circuit layer and a hole wall of the hole. During a packaging process, the design of the solder stand increases a contact area of a solder tin ball with a metal material. Therefore, a bonding force between the solder tin ball and the solder stand is increased, and the solder tin ball can be protected from being broken or fell off. An electronic package having the semiconductor packaging substrate and a method for fabricating the electronic package are also provided.
    Type: Application
    Filed: March 27, 2020
    Publication date: October 1, 2020
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Patent number: 10784205
    Abstract: An electronic package is provided, which includes: an insulating layer; an electronic element embedded in the insulating layer and having a sensing area exposed from the insulating layer; and a circuit layer formed on the insulating layer and electrically connected to the electronic element, thereby reducing the thickness of the overall package structure.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: September 22, 2020
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chu-Chin Hu, Shih-Ping Hsu
  • Patent number: 10745818
    Abstract: This disclosure provides a package substrate fabrication method including: providing a carrier; forming a first dielectric layer on the carrier while enabling the first dielectric layer to be patterned including an opening; forming a first conducting unit on the carrier while enabling the first conducting unit to fill up the opening, a height of the first conducting unit at the opening larger than a thickness of the first dielectric layer, and a width of the first conducting unit larger than a width of the opening; forming a second dielectric layer on the first conducting unit; forming a second conducting unit on the second dielectric layer; forming a third dielectric layer on the second conducting unit; removing the carrier and the first dielectric layer while enabling the part of the first conducting unit in the opening to be removed; and forming a fourth dielectric layer to cover the first conducting unit.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: August 18, 2020
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Pao-Hung Chou
  • Publication number: 20200161234
    Abstract: A semiconductor package structure includes a chip, a conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with at least a first metal electrode pad and a second side with at least a second metal electrode pad. The conductive pillar, which has a first end and a second end, is disposed adjacent to the chip. The axis direction of the conductive pillar is parallel to the height direction of the chip. The dielectric layer covers the chip and the conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 21, 2020
    Inventors: Che-Wei Hsu, Shih-Ping Hsu, Chao-Tsung Tseng
  • Publication number: 20200153409
    Abstract: A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 14, 2020
    Inventors: Shih-Ping Hsu, Che-Wei Hsu
  • Publication number: 20200135693
    Abstract: A semiconductor package structure includes a circuit build-up substrate, a chip, a plurality of conductive pillar, a molding layer and at least a memory module. The circuit build-up substrate has a first surface. A plurality of flip-chip bonding pads and a plurality of first bonding pads are exposed from the first surface. The chip is electrically connected to the flip-chip bonding pads. The conductive pillars are disposed on the first surface of the circuit build-up substrate and electrically connected to the first bonding pads. The molding layer is disposed on the first surface of the circuit build-up substrate to cover the chip and the conductive pillars. A second side of the chip and a first end of each conductive pillar are exposed from the molding layer. The memory module is disposed on the molding layer and electrically connected to the first end of the conductive pillar.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 30, 2020
    Inventors: Chu-Chin Hu, Shih-Ping Hsu, Che-Wei Hsu
  • Publication number: 20200075554
    Abstract: An electronic package includes a circuit structure having a first electronic component disposed on one side thereof, and a second electronic component and conductive pillars disposed on the other side thereof. The second electronic component and the conductive pillars are encapsulated by an encapsulant, and end faces of the conductive pillars are exposed from the encapsulant, allowing the exposed end faces to be connected to an external circuit board. As the end faces of the conductive pillars are used as contact structures, fine-pitch electronic packages can be achieved. Also, by providing sufficient space attributed to the tall columnar structures of the conductive pillars, the second electronic component of an appropriate thickness can be obtained, allowing the electronic package to be suitable for applications requiring high voltages and/or high currents. A method for fabricating an electronic package is further provided.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Inventors: Che-Wei Hsu, Chu-Chin Hu, Shih-Ping Hsu
  • Publication number: 20200075565
    Abstract: A package structure for a semiconductor device includes a first conductive layer, a second conductive layer, a first die, a second die, a plurality of first blind via pillars and a conductive structure. The first conductive layer has a first surface and a second surface. The first die and the second die respectively have an active surface and a back surface, which are disposed opposite to each other. There is a plurality of metal pads disposed on the active surface. The first die is attached to the first surface of the first conductive layer with its back surface, and the second die is attached to the second surface of the first conductive layer with its back surface. The first and second conductive layers, the first and second dies, the first blind hole pillars and conductive structure are covered by a dielectric material.
    Type: Application
    Filed: August 12, 2019
    Publication date: March 5, 2020
    Inventors: Che-Wei Hsu, Shih-Ping Hsu
  • Patent number: 10580739
    Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate includes: a molding compound body; a first circuit device disposed in the molding compound body, the first circuit device having a first terminal at a top of the first circuit device; a first conductive via formed in the molding compound body and connected to the first terminal; a second circuit device disposed in the molding compound body, the second circuit device having a second terminal at a top of the second circuit device; a second conductive via formed in the molding compound body and connected to the second terminal; and a redistribution layer with a conductive wire formed on the molding compound body, the conductive wire connecting the first conductive via and the second conductive via; wherein the first and second terminals are respectively located at different depths of the molding compound body.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: March 3, 2020
    Assignee: PHOENIX & CORPORATION
    Inventors: Chu-Chin Hu, Shih-Ping Hsu
  • Publication number: 20200066624
    Abstract: A flip-chip package substrate and a method for preparing the same in accordance with the present disclosure includes stacking a reinforcement layer on two opposing sides of a core layer in order to increase the rigidity of the flip-chip package substrate, and promoting a thin core layer, wherein the sizes of the end faces of conductive portions can be minimized according to needs. This increases the number of electrical contacts possible in a unit area and enables the creation of finer line pitch and higher layout density of the circuit portions, thereby satisfying the need for packaging of high integration/large scale chips while preventing warpage from occurring in the electronic packages.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 27, 2020
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Patent number: 10483194
    Abstract: The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 19, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Shih-Ping Hsu
  • Patent number: 10483232
    Abstract: A method for fabricating bump structures on chips with a panel type process is provided. First, a panel type substrate is provided. Semiconductor chips are fixed on the panel type substrate. Each semiconductor chip includes metal pads and a passivation layer exposing the metal pads. At least an electroless plating process is performed to form under bump metallurgy structures on the metal pads. The method simplifies the processes of forming electrical connections for semiconductor chips. The panel type process can effectively increase the yield, and reduce the manufacturing cost.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 19, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Shih-Ping Hsu, Che-Wei Hsu, Tung-Yao Kuo
  • Publication number: 20190348375
    Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 14, 2019
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
  • Patent number: 10475765
    Abstract: The disclosure provides an interposer substrate and a method for manufacturing the same. The method includes forming an insulating protection layer having a phosphorus compound on a substrate body, thereby providing toughness and strength as required when the thickness of the interposer substrate becomes too thin, and preventing substrate warpage when the substrate has a shrinkage stress or structural asymmetries.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: November 12, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Shih-Ping Hsu, Che-Wei Hsu, Ching-Chieh Chang, Chao-Chung Tseng