Patents by Inventor Shih-Ping Hsu
Shih-Ping Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12204163Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: February 5, 2024Date of Patent: January 21, 2025Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 12202899Abstract: An anti-PD-L1 antibody, or an antigen-binding fragment thereof, comprising: a heavy chain variable region comprising the three CDRs with the sequences of SEQ ID NOs: 2-4, 6-8, 10-12, 14-16, or 18-20; and/or a light chain variable region comprising the three CDRs with the sequences of SEQ ID NOs: 22-24, 26-28, 30-32, 34-36, or 38-40, wherein the antibody is a chimeric, humanized, composite, or human antibody.Type: GrantFiled: July 14, 2019Date of Patent: January 21, 2025Assignee: Development Center for BiotechnologyInventors: Cheng-Chou Yu, Shih-Rang Yang, Tsung-Han Hsieh, Mei-Chi Chan, Shu-Ping Yeh, Chuan-Lung Hsu, Ling-Yueh Hu, Chih-Lun Hsiao
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Patent number: 12154866Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.Type: GrantFiled: August 19, 2022Date of Patent: November 26, 2024Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
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Patent number: 12094922Abstract: An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.Type: GrantFiled: March 4, 2022Date of Patent: September 17, 2024Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
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Patent number: 12062685Abstract: An inductor structure is provided. A plurality of first and second conductive posts have end surfaces corresponding in profile to ends of first conductive sheets, respectively. As such, the profiles of the end surfaces of the first and second conductive posts are non-cylindrical so as to increase the contact area between the first conductive sheets and the first and second conductive posts, thereby improving the conductive quality and performance of the inductor. Further, since the first and second conductive posts are formed by stacking a plurality of post bodies on one another, the number and cross-sectional area of loops are increased so as to increase the inductance value. A method for fabricating the inductor structure, an electronic package and a fabrication method thereof, and a method for fabricating a packaging carrier are further provided.Type: GrantFiled: January 28, 2022Date of Patent: August 13, 2024Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventor: Shih-Ping Hsu
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Publication number: 20240235046Abstract: An antenna module is provided, in which an antenna supporting substrate having a step-shaped hollow cavity is disposed on a circuit structure having an antenna part, so that the antenna part is exposed from the step-shaped hollow cavity, and an antenna structure is arranged on the steps of the step-shaped hollow cavity to cover the antenna part and is electromagnetically coupled with the antenna part, and there is no barrier but an air medium between the antenna structure and the antenna part.Type: ApplicationFiled: September 5, 2023Publication date: July 11, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung CHOU, Shih-Ping HSU
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Publication number: 20240222140Abstract: A package carrier board includes a first circuit build-up structure, a patterned magnetic conductive metal layer, a plurality of first conductive pillar, a second insulating layer, and a second circuit build-up structure. The patterned magnetic conductive metal layer is disposed above the first circuit build-up structure, and the cross-sectional pattern of the patterned magnetic conductive metal layer is L-shaped and/or U-shaped. The first conductive pillars are disposed on the first circuit build-up structure and located outside of the patterned magnetic conductive metal layer. The second insulating layer covers the patterned magnetic conductive metal layer and the first conductive pillars. The second circuit build-up structure is disposed on the second insulating layer. The first circuit build-up structure, the first conductive pillars, the second insulating layer, and the second circuit build-up structure are combined to form an inductive circuit structure.Type: ApplicationFiled: December 22, 2023Publication date: July 4, 2024Inventors: Che-Wei HSU, Pao-Hung CHOU, Shih-Ping HSU
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Publication number: 20240215174Abstract: The invention provides a package carrier board and a manufacturing method thereof. The packaging carrier board includes a core layer, a magnetic element structure and a conductive connecting element. The core layer has a first surface and a second surface opposite to each other. The magnetic element structure includes a plurality of patterned magnetic conductive metal layers and a plurality of patterned conductive coil layers. The patterned magnetic conductive metal layers are stacked and embedded in the core layer, and each have at least one magnetic conductive metal, and part of these magnetic conductive metals form an array block. The patterned conductive coil layers are embedded in the core layer, and part of the patterned conductive coil layers are located on both sides of the array block. The conductive connecting element is arranged through the core layer and conducts the first surface and the second surface of the core layer.Type: ApplicationFiled: March 15, 2023Publication date: June 27, 2024Inventor: Shih-Ping Hsu
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Publication number: 20240195047Abstract: The invention discloses a semiconductor package antenna structure and its manufacturing method, wherein the semiconductor package antenna structure includes a first substrate, a semiconductor chip, and a second substrate. The first substrate has at least two stacked first redistribution layers, and each of the first redistribution layers has a first dielectric layer, a first patterned metal layer, and/or a first conductive pillar layer. The semiconductor chip is embedded in the first substrate and coupled to the first redistribution layers. The second substrate has a second redistribution layer, a second conductive pillar layer, and an air dielectric layer, wherein the second conductive pillar layer is protruded from the second redistribution layer. The second substrate is connected to the first substrate by a second conductive pillar layer, and the air dielectric layer is located between the second redistribution layer, the second conductive pillar layer, and the first substrate.Type: ApplicationFiled: November 27, 2023Publication date: June 13, 2024Inventors: Che-Wei Hsu, Shih-Ping Hsu
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Publication number: 20240194386Abstract: An inductor structure is provided, in which an inductance coil in the shape of a toroidal coil or a helical coil is arranged in an insulator, and a magnetically permeable body made of a magnetically permeable material is a multi-layer stacked structure and arranged in the inductance coil, where the magnetically permeable body is free from being electrically connected to the inductance coil. Therefore, the magnetically permeable body made of a magnetically permeable material in the form of a multi-layer stacked structure may effectively improve the electrical characteristics of the inductor structure.Type: ApplicationFiled: December 8, 2023Publication date: June 13, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Shih-Ping HSU, Pao-Hung CHOU
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Publication number: 20240161957Abstract: Provided is an inductor structure and manufacturing method thereof, including forming an inductance coil in a semiconductor packaging carrier plate and disposing a patterned magnetic conductive layer in the inductance coil. Therefore, a patterned build-up wiring method is used to form a magnetic material in the carrier plate, thereby improving electrical characteristics of the inductor.Type: ApplicationFiled: October 31, 2023Publication date: May 16, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung CHOU, Shih-Ping HSU, Chu-Chin HU
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Publication number: 20240145155Abstract: Provided is a core structure of an inductor element. The manufacturing method thereof is to embed a magnetic conductor including at least one magnetic conductive layer in a core body and to from a plurality of apertures for passing coils around the magnetic conductor in the core body. Accordingly, the magnetic conductor is designed in the core body by using the integrated circuit carrier board manufacturing process, such that the overall size and thickness of the inductor element can be greatly reduced, thereby facilitating product miniaturization using the inductor element.Type: ApplicationFiled: October 31, 2023Publication date: May 2, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung CHOU, Che-Wei HSU, Shih-Ping HSU
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Publication number: 20240136728Abstract: An antenna module is provided, in which an antenna supporting substrate having a step-shaped hollow cavity is disposed on a circuit structure having an antenna part, so that the antenna part is exposed from the step-shaped hollow cavity, and an antenna structure is arranged on the steps of the step-shaped hollow cavity to cover the antenna part and is electromagnetically coupled with the antenna part, and there is no barrier but an air medium between the antenna structure and the antenna part.Type: ApplicationFiled: September 4, 2023Publication date: April 25, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung CHOU, Shih-Ping HSU
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Publication number: 20240128005Abstract: The invention provides an electronic device and its manufacturing method. The electronic device includes a first conductive component, which includes a first seed layer, a first conductive layer, a first conductive thickening layer, and a first insulating layer. The first seed layer has a plurality of first seed blocks. The first conductive layer has a plurality of first conductive blocks. Each of the first conductive blocks is disposed on a top surface of the first seed block, respectively. The first conductive thickening layer has a plurality of first conductive thickened blocks, which covers one side surface of each first seed block and one side surface of each first conductive block respectively. The first insulating layer covers the first seed layer, the first conductive layer, and the first conductive thickening layer.Type: ApplicationFiled: September 8, 2023Publication date: April 18, 2024Inventor: Shih-Ping Hsu
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Publication number: 20240096838Abstract: A component-embedded packaging structure is provided, in which a plurality of metal layers are formed on an inactive surface of a semiconductor chip so as to serve as a buffer portion, and the semiconductor chip is disposed on a carrying portion with the buffer portion via an adhesive. Then, the semiconductor chip is encapsulated by an insulating layer, and a build-up circuit structure is formed on the insulating layer and electrically connected to the semiconductor chip. Therefore, the buffer portion can prevent delamination from occurring between the semiconductor chip and the adhesive on the carrying portion if the semiconductor chip has a CTE (Coefficient of Thermal Expansion) less than a CTE of the adhesive.Type: ApplicationFiled: September 18, 2023Publication date: March 21, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chu-Chin HU, Shih-Ping HSU, Chih-Kuai YANG
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Patent number: 11757426Abstract: A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.Type: GrantFiled: June 6, 2022Date of Patent: September 12, 2023Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Shih-Ping Hsu, Che-Wei Hsu
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Patent number: 11749612Abstract: A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.Type: GrantFiled: November 29, 2021Date of Patent: September 5, 2023Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Hsien-Ming Tsai
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Patent number: 11658104Abstract: An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.Type: GrantFiled: February 24, 2022Date of Patent: May 23, 2023Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Shih-Ping Hsu, Chu-Chin Hu, Pao-Hung Chou
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Patent number: 11552014Abstract: A semiconductor package structure includes a chip, a conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with at least a first metal electrode pad and a second side with at least a second metal electrode pad. The conductive pillar, which has a first end and a second end, is disposed adjacent to the chip. The axis direction of the conductive pillar is parallel to the height direction of the chip. The dielectric layer covers the chip and the conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar.Type: GrantFiled: November 7, 2019Date of Patent: January 10, 2023Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Che-Wei Hsu, Shih-Ping Hsu, Chao-Tsung Tseng
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Publication number: 20220406734Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.Type: ApplicationFiled: August 19, 2022Publication date: December 22, 2022Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo