Patents by Inventor Shih-Ting Lin

Shih-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10325991
    Abstract: The present disclosure provides a transistor device. The transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: June 18, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shih-Ting Lin, Jhen-Yu Tsai
  • Publication number: 20190178931
    Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.
    Type: Application
    Filed: March 5, 2018
    Publication date: June 13, 2019
    Inventors: Shih-Ting LIN, Kung-Ming FAN, Hung-Hsiang XSIAO
  • Publication number: 20190172919
    Abstract: A transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 6, 2019
    Inventors: SHIH-TING LIN, JHEN-YU TSAI
  • Publication number: 20190173469
    Abstract: The present disclosure provides a transistor device. The transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.
    Type: Application
    Filed: January 3, 2018
    Publication date: June 6, 2019
    Inventors: Shih-Ting Lin, Jhen-Yu Tsai
  • Publication number: 20190172918
    Abstract: The present disclosure provides a transistor device. The transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.
    Type: Application
    Filed: August 31, 2018
    Publication date: June 6, 2019
    Inventors: Shih-Ting Lin, Jhen-Yu Tsai
  • Publication number: 20190164720
    Abstract: A liquid sample carrier includes a first base that includes a first carrying portion having a first sample holding surface, and a second base that is connectable to the first base and that includes a second carrying portion, a support layer, and a second sample holding surface. The second carrying portion is stackable on the first carrying portion, and has a surrounding wall defining a through hole. The support layer is connected to the second carrying portion and has a window area corresponding to the through hole, and a peripheral area surrounding the window area. The second sample holding surface is connected to the support layer. A sample receiving area is formed between the first and second sample holding surfaces.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: Po-Tsung Hsieh, Chung-Jen Chung, Shih-Wen Tseng, Tzu-Ting Tsai, Chih-Chien Lin, Wen-Kuei Chuang
  • Publication number: 20190165178
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: October 31, 2018
    Publication date: May 30, 2019
    Inventors: Chih-Liang CHEN, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Shih-Wei Peng, Wei-Cheng Lin, Lei-Chun Chou
  • Publication number: 20190157405
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.
    Type: Application
    Filed: May 30, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
  • Patent number: 10297588
    Abstract: A semiconductor device includes at least one first gate strip, at least one second gate strip, at least one first conductive line and at least one first conductive via. An end surface of the at least one first gate strip and an end surface of the at least one second gate strip are opposite each other. The at least one first conductive line is over the at least one first gate strip and the at least one second gate strip and across the end surface of the at least one first gate strip and the end surface of the at least one second gate strip. The at least one first conductive via connects the at least one first conductive line and the at least one first gate strip.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Cheng Lin, Hui-Ting Yang, Shih-Wei Peng, Jiann-Tyng Tzeng, Charles Chew-Yuen Young, Chih-Ming Lai
  • Publication number: 20190148435
    Abstract: A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih Pei Chou, Min-Feng Kao, Szu-Ying Chen
  • Publication number: 20190148556
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.
    Type: Application
    Filed: July 24, 2018
    Publication date: May 16, 2019
    Inventors: Chun-Chieh WANG, Yu-Ting LIN, Yueh-Ching PAI, Shih-Chieh CHANG, Huai-Tei YANG
  • Patent number: 10290513
    Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jing-Cheng Lin, Shih Ting Lin, Chen-Hua Yu
  • Patent number: 10269762
    Abstract: A rework process includes attaching a first bond head to a first semiconductor package. The contact pads of the first semiconductor package are bonded to contact pads of a second semiconductor package by solder joints. The rework process further includes performing a first local heating process to melt the solder joints, removing the first semiconductor package using the first bond head, and removing at least a portion of solder from the contact pads of the second semiconductor package.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Ting Lin, Justin Huang, Tsung-Fu Tsai, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 10203252
    Abstract: A MEMS apparatus having measuring range selector including a sensor and an IC chip is provided. The sensor includes a sensing device. The IC chip includes a voltage range selector, an analog front end, a control device and an A/D converter. The sensing device is configured to detect the physical quantity and generate a sensing voltage. The voltage range selector is configured to select a sub-voltage range having a first upper-bound and a first lower-bound. The analog front end is configured to receive the sensing voltage and output a first voltage. The A/D converter has a full scale voltage range having a second lower-bound and a second upper-bound. A ratio of the full scale voltage range to the sub-voltage range is defined as a gain factor. A difference obtained by subtracting the first lower-bound from the first voltage is defined as a shift factor. The control device is configured to adjust the first voltage to the second voltage according to the gain factor and the shift factor.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 12, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Wen Hsu, Feng-Chia Hsu, Chao-Ta Huang, Shih-Ting Lin
  • Publication number: 20180366439
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Tsung-Fu Tsai, Chen-Hua Yu, Po-Hao Tsai, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai, Chen-Hsuan Tsai
  • Patent number: 10157888
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Tsung-Fu Tsai, Chen-Hua Yu, Po-Hao Tsai, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai, Chen-Hsuan Tsai
  • Patent number: 10153179
    Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jing-Cheng Lin, Shih Ting Lin, Chen-Hua Yu
  • Publication number: 20180337137
    Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 22, 2018
    Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu
  • Publication number: 20180337065
    Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Jing-Cheng Lin, Shih Ting Lin, Chen-Hua Yu
  • Publication number: 20180188115
    Abstract: A MEMS apparatus having measuring range selector including a sensor and an IC chip is provided. The sensor includes a sensing device. The IC chip includes a voltage range selector, an analog front end, a control device and an A/D converter. The sensing device is configured to detect the physical quantity and generate a sensing voltage. The voltage range selector is configured to select a sub-voltage range having a first upper-bound and a first lower-bound. The analog front end is configured to receive the sensing voltage and output a first voltage. The A/D converter has a full scale voltage range having a second lower-bound and a second upper-bound. A ratio of the full scale voltage range to the sub-voltage range is defined as a gain factor. A difference obtained by subtracting the first lower-bound from the first voltage is defined as a shift factor. The control device is configured to adjust the first voltage to the second voltage according to the gain factor and the shift factor.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Wen Hsu, Feng-Chia Hsu, Chao-Ta Huang, Shih-Ting Lin