Patents by Inventor Shih-Ting Lin
Shih-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11411161Abstract: A piezoelectric system comprises a piezoelectric sensor, a voltage stabilizer, a discharger and an operation sensor. The piezoelectric sensor outputs a sensing signal through a sensor output terminal according to a rate of change of pressure. The voltage stabilizer has a positive terminal electrically connecting with the sensor output terminal. The voltage stabilizer receives the sensing signal, stores the energy of the sensing signal, and keeps the voltage of the sensing signal as a constant when the rate of change of pressure is zero. The discharger has a first terminal connecting with the positive terminal, a second terminal coupled to ground, and a control terminal receiving a trigger signal to control the first terminal to conduct with or not conduct with the second terminal. The operation sensor electrically connects to the control terminal for sensing an operation generating the pressure and outputs the trigger signal accordingly.Type: GrantFiled: April 15, 2020Date of Patent: August 9, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Hsiou Lin, Shih-Ting Lin, Chung-Yuan Su, Chao-Ta Huang
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Publication number: 20220187149Abstract: A spindle shaft device including a shaft, a first torque sensor, and a second torque sensor. The shaft extends along an axial direction and comprises a first side portion, a second side portion, and a central portion located between the first side portion and the second side portion. The central portion has a central torsional rigidity with respect to the axial direction. The first side portion has a first torsional rigidity with respect to the axial direction. The second side portion has a second torsional rigidity with respect to the axial direction. The first torsional rigidity is smaller than the central torsional rigidity. The second torsional rigidity is smaller than the central torsional rigidity. The first torque sensor is disposed on the first side portion. The second torque sensor is disposed on the second side portion.Type: ApplicationFiled: April 19, 2021Publication date: June 16, 2022Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Nan YEH, Pei-Yu CHANG, Shih-Ting LIN, Chao-Ta HUANG
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Patent number: 11355454Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The semiconductor device is disposed on the second surface of the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is directly in contact with the insulating encapsulation.Type: GrantFiled: July 30, 2020Date of Patent: June 7, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
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Publication number: 20220131326Abstract: A laser inspection system is provided. A laser source emits a laser with a first spectrum and the laser is transmitted by a first optical fiber. A gain optical fiber doped with special ions is connected to the first optical fiber, and a light detector is provided around the gain optical fiber. When the laser with the first spectrum passes through the gain optical fiber, the gain optical fiber absorbs part of the energy level of the laser with the first spectrum, so that the laser with the first spectrum is converted to generate light with a second spectrum based on the frequency conversion phenomenon. The light detector detects the intensity of the light with the second spectrum, so that the power of the laser source can be obtained.Type: ApplicationFiled: November 23, 2020Publication date: April 28, 2022Inventors: Yi-Chi Lee, Hsin-Chia Su, Shih-Ting Lin, Yu-Cheng Song, Fu-Shun Ho, Chih-Chun Chen
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Patent number: 11282793Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.Type: GrantFiled: July 26, 2018Date of Patent: March 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu
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Publication number: 20220068856Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.Type: ApplicationFiled: December 31, 2020Publication date: March 3, 2022Inventors: Wen-Chih Chiou, Chen-Hua Yu, Shih Ting Lin, Szu-Wei Lu
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Publication number: 20220047857Abstract: A manufacturing method for a micro-needle device includes following steps: a target tissue basic information obtaining step, a micro-needle template obtaining step, a micro-needle material adding step, a micro-needle semi-product obtaining step, and a micro-needle device obtaining step. The inner tissue distribution information is obtained by the application of optical coherence tomography. The micro-needle template is obtained according to the skin surface curvature information and the inner tissue distribution information. The micro-needle template has a plurality of areas and a plurality of mold holes. One or both of the diameter and the depth of the mold hole is determined by the inner tissue distribution information, and the curvature radius of the areas is determined by the skin surface curvature information. The manufacturing method for a micro-needle device is applicable to micro-needles with mixed configurations as well as micro-needles with syringe configurations.Type: ApplicationFiled: October 30, 2020Publication date: February 17, 2022Applicant: Tamkang UniversityInventors: Ming-Kai Chern, Man-Piu Chan, Yueh-Tzu Lo, I-Chang Liu, Shih-Ting Lin, You-Lin Wei, Wen-Chi Chou, Wen-Hua Chuang, Yin-Jun Wu, Hun-Boa Wang, Bo-Cheng Wang
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Publication number: 20220037266Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The semiconductor device is disposed on the second surface of the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is directly in contact with the insulating encapsulation.Type: ApplicationFiled: July 30, 2020Publication date: February 3, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
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Patent number: 11205629Abstract: A package structure including a wiring substrate, conductive terminals, an insulating encapsulation, a redistribution circuit structure, guiding patterns and a semiconductor device. The conductive terminals are disposed on a surface of the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate and the conductive terminals. The redistribution circuit structure is disposed on the insulating encapsulation and the conductive terminals, and the redistribution circuit structure is electrically connected to the wiring substrate through the conductive terminals. The guiding patterns are disposed between the wiring substrate and the redistribution circuit structure, and the guiding patterns are in contact with and encapsulated by the insulating encapsulation.Type: GrantFiled: April 8, 2020Date of Patent: December 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu
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Publication number: 20210384044Abstract: A method of fabricating a semiconductor device is provided, including providing a base substrate and a die stacking unit mounted on the base substrate. Conductive joints are connected between two adjacent dies of the die stacking unit. The method further includes providing dummy micro bumps and dummy pads between the two adjacent dies and between the conductive joints. The dummy micro bumps and the dummy pads are connected to one of the two adjacent dies but not to the other, and the dummy micro bumps are formed on some of the dummy pads but not on all of the dummy pads. In addition, the method includes filling the gaps between the base substrate, all dies of the die stacking unit, the conductive joints, the dummy micro bumps, and the dummy pads with an underfill material by capillary attraction.Type: ApplicationFiled: August 20, 2021Publication date: December 9, 2021Inventors: Tsung-Fu TSAI, Chen-Hsuan TSAI, Chung-Chieh TING, Shih-Ting LIN, Szu-Wei LU
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Patent number: 11133289Abstract: A semiconductor package includes a first integrated circuit structure, a second integrated circuit structure, a plurality of conductive bumps, an encapsulating material, and a redistribution structure. The first integrated circuit structure includes an active surface having a plurality of contact pads, a back surface opposite to the active surface, and a plurality of through vias extending through the first integrated circuit structure and connecting the active surface and the back surface. The second integrated circuit structure is disposed on the back surface of the first integrated circuit structure. The conductive bumps are disposed between the first integrated circuit structure and the second integrated circuit structure, and electrically connecting the plurality of through vias and the second integrated circuit structure. The encapsulating material at least encapsulates the second integrated circuit structure.Type: GrantFiled: May 16, 2019Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Ying-Ching Shih
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Patent number: 11101252Abstract: A package-on-package structure including a first and second package is provided. The first package includes a semiconductor die, through insulator vias, an insulating encapsulant, conductive terminals and a redistribution layer. The semiconductor die has a die height H1. The plurality of through insulator vias is surrounding the semiconductor die and has a height H2, and H2<H1. The insulating encapsulant is encapsulating the semiconductor die and the plurality of through insulator vias, wherein the insulating encapsulant has a plurality of via openings revealing each of the through insulator vias. The plurality of conductive terminals is disposed in the via openings and electrically connected to the plurality of through insulator vias. The redistribution layer is disposed on the active surface of the semiconductor die and over the insulating encapsulant. The second package is stacked on the first package and electrically connected to the plurality of conductive terminals of the first package.Type: GrantFiled: August 22, 2019Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Ting Lin, Chin-Fu Kao, Jing-Cheng Lin, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11101145Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate, a die stacking unit, a number of dummy micro bumps, and an underfill material. The die stacking unit, which is mounted on the base substrate, includes a first die, a second die, and a number of first conductive joints. The first die and the second die are stacked on each other, and the first conductive joints are disposed between and connected to the first die and the second die. The dummy micro bumps, which are disposed between the first conductive joints, are connected to the first die but not to the second die. The underfill material is filled into a number of gaps between the base substrate, the first die, the second die, the first conductive joints, and the dummy micro bumps.Type: GrantFiled: November 1, 2018Date of Patent: August 24, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Fu Tsai, Chen-Hsuan Tsai, Chung-Chieh Ting, Shih-Ting Lin, Szu-Wei Lu
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Publication number: 20210242177Abstract: A package structure is provided. The package structure includes a substrate and a stack of semiconductor dies over the substrate. The package structure also includes an underfill element covering sidewalls of the semiconductor dies. The package structure further includes a protective film attached to the substrate and laterally surrounding the underfill element and the semiconductor dies. The underfill element separates the protective film from the semiconductor dies.Type: ApplicationFiled: April 19, 2021Publication date: August 5, 2021Inventors: Chen-Hsuan TSAI, Tsung-Fu TSAI, Shih-Ting LIN, Szu-Wei LU
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Publication number: 20210225666Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: Shih Ting Lin, Szu-Wei Lu, Weiming Chris Chen, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20210225791Abstract: A package structure including a wiring substrate, conductive terminals, an insulating encapsulation, a redistribution circuit structure, guiding patterns and a semiconductor device. The conductive terminals are disposed on a surface of the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate and the conductive terminals. The redistribution circuit structure is disposed on the insulating encapsulation and the conductive terminals, and the redistribution circuit structure is electrically connected to the wiring substrate through the conductive terminals. The guiding patterns are disposed between the wiring substrate and the redistribution circuit structure, and the guiding patterns are in contact with and encapsulated by the insulating encapsulation.Type: ApplicationFiled: April 8, 2020Publication date: July 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu
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Patent number: 11056436Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.Type: GrantFiled: June 7, 2016Date of Patent: July 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu
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Publication number: 20210202822Abstract: A piezoelectric system comprises a piezoelectric sensor, a voltage stabilizer, a discharger and an operation sensor. The piezoelectric sensor outputs a sensing signal through a sensor output terminal according to a rate of change of pressure. The voltage stabilizer has a positive terminal electrically connecting with the sensor output terminal. The voltage stabilizer receives the sensing signal, stores the energy of the sensing signal, and keeps the voltage of the sensing signal as a constant when the rate of change of pressure is zero. The discharger has a first terminal connecting with the positive terminal, a second terminal coupled to ground, and a control terminal receiving a trigger signal to control the first terminal to conduct with or not conduct with the second terminal. The operation sensor electrically connects to the control terminal for sensing an operation generating the pressure and outputs the trigger signal accordingly.Type: ApplicationFiled: April 15, 2020Publication date: July 1, 2021Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Hsiou LIN, Shih-Ting LIN, Chung-Yuan SU, Chao-Ta HUANG
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Publication number: 20210193577Abstract: Package structure and method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge die, and a second encapsulant. The first encapsulant laterally encapsulates the first die and the second die. The bridge die is electrically connected to the first die and the second die. The second encapsulant is located over the first die, the second die and the first encapsulant, laterally encapsulating the bridge die and filling a space between the bridge die and the first die, between the bridge die and the first encapsulant and between the bridge die and the second die. A material of the second encapsulant is different from a material of the first encapsulant.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Ting Lin, Szu-Wei Lu
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Publication number: 20210167024Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure. The first stacked die package structure includes a plurality of memory dies. The underfill layer is over the first stacked die package structure. The underfill layer includes a first protruding portion that extends below a top surface of the through substrate via structure. The package layer is over the underfill layer. The package layer has a second protruding portion that extends below the top surface of the through substrate via structure.Type: ApplicationFiled: February 9, 2021Publication date: June 3, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu TSAI, Kung-Chen YEH, I-Ting HUANG, Shih-Ting LIN, Szu-Wei LU