Abstract: The present disclosure provides a transistor device. The transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.

Abstract: A package-on-package structure including a first and second package is provided. The first package includes a semiconductor die, through insulator vias, an insulating encapsulant, conductive terminals and a redistribution layer. The semiconductor die has a die height H1. The plurality of through insulator vias is surrounding the semiconductor die and has a height H2, and H2<H1. The insulating encapsulant is encapsulating the semiconductor die and the plurality of through insulator vias, wherein the insulating encapsulant has a plurality of via openings revealing each of the through insulator vias. The plurality of conductive terminals is disposed in the via openings and electrically connected to the plurality of through insulator vias. The redistribution layer is disposed on the active surface of the semiconductor die and over the insulating encapsulant. The second package is stacked on the first package and electrically connected to the plurality of conductive terminals of the first package.

Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.

Abstract: The present disclosure provides a transistor device. The transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.

Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.

Abstract: The present disclosure provides a transistor device. The transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.

Abstract: A transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.

Abstract: The present disclosure provides a transistor device. The transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.

Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

Abstract: A rework process includes attaching a first bond head to a first semiconductor package. The contact pads of the first semiconductor package are bonded to contact pads of a second semiconductor package by solder joints. The rework process further includes performing a first local heating process to melt the solder joints, removing the first semiconductor package using the first bond head, and removing at least a portion of solder from the contact pads of the second semiconductor package.

Abstract: A MEMS apparatus having measuring range selector including a sensor and an IC chip is provided. The sensor includes a sensing device. The IC chip includes a voltage range selector, an analog front end, a control device and an A/D converter. The sensing device is configured to detect the physical quantity and generate a sensing voltage. The voltage range selector is configured to select a sub-voltage range having a first upper-bound and a first lower-bound. The analog front end is configured to receive the sensing voltage and output a first voltage. The A/D converter has a full scale voltage range having a second lower-bound and a second upper-bound. A ratio of the full scale voltage range to the sub-voltage range is defined as a gain factor. A difference obtained by subtracting the first lower-bound from the first voltage is defined as a shift factor. The control device is configured to adjust the first voltage to the second voltage according to the gain factor and the shift factor.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.

Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.

Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

Abstract: A MEMS apparatus having measuring range selector including a sensor and an IC chip is provided. The sensor includes a sensing device. The IC chip includes a voltage range selector, an analog front end, a control device and an A/D converter. The sensing device is configured to detect the physical quantity and generate a sensing voltage. The voltage range selector is configured to select a sub-voltage range having a first upper-bound and a first lower-bound. The analog front end is configured to receive the sensing voltage and output a first voltage. The A/D converter has a full scale voltage range having a second lower-bound and a second upper-bound. A ratio of the full scale voltage range to the sub-voltage range is defined as a gain factor. A difference obtained by subtracting the first lower-bound from the first voltage is defined as a shift factor. The control device is configured to adjust the first voltage to the second voltage according to the gain factor and the shift factor.

Abstract: Disclosed is a laser system and a laser flare machining method. The laser system includes a laser light source, a splitter element, and a scanning lens assembly. The laser light source projects a first light beam. The splitter element is furnished on a first path along which the first light beam travels, and splits the first light beam into a second light beam traveling along a second path and a third light beam traveling along a third path. The scanning lens assembly is furnished on the second path and the third path, and focus the second light beam and the third light beam at a machining position to process a work piece.

Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.