Patents by Inventor Shih-Wei Chou
Shih-Wei Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250227325Abstract: A server comprising a circuitry, wherein the circuitry is configured to perform: generating an emulator in response to a request from a first user terminal of a first user; launching an application via the emulator; receiving streaming data and interaction data via the application; rendering the streaming data with the interaction data; recording the rendered streaming data and interaction data as a clip; and storing the clip for access from the first user terminal of the first user. According to the present disclosure, the clips may be generated in a more efficient and accurate manner, and a more immersive experience on watching the clips may be provided. Moreover, the review and share of clips may be more flexible. Therefore, the user experience may be improved.Type: ApplicationFiled: January 6, 2025Publication date: July 10, 2025Inventors: Kun-Ze LI, Che-Wei LIU, You-Chang LIN, Chieh-Min CHEN, Hao-Chia CHUNG, Yu-Cheng FAN, Chia-Yi YEH, Yu-Chuan CHANG, Chi-Hao HSIEH, Yung-Chi HSU, Po-Kao TSENG, Chien-Ming LAI, Shih-Wei CHOU
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Publication number: 20250211414Abstract: Embodiments herein describe techniques for area and power efficient clock data recovery (CDR) and adaptation implementations for dense wavelength-division multiplexing (DWDM) optical links and other types of links. One example is a system that includes a plurality of receiver circuits that sample signals based on respective receiver clocks, where the receiver circuits include a reference receiver circuit and remaining receiver circuits, and where the receiver clock of the reference receiver circuit comprises a reference clock.Type: ApplicationFiled: December 22, 2023Publication date: June 26, 2025Inventors: Chi Fung POON, Shih-Wei CHOU, Mayank RAJ, Parag UPADHYAYA, Huy NGO, Weisheng Winson LIN
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Patent number: 11838000Abstract: Aspects of the present disclosure provide a method for regulating an integration current of a sensing amplifier. The sensing amplifier includes a first input transistor and a second input transistor, wherein a source of the first input transistor and a source of the second input transistor are coupled to a source node. The method includes pulling a current from or sourcing the current to the source node, measuring the integration current, comparing the measured integration current with a reference signal, and adjusting the current pulled from or sourced to the source node based on the comparison.Type: GrantFiled: November 8, 2021Date of Patent: December 5, 2023Assignee: QUALCOMM INCORPORATEDInventors: Todd Morgan Rasmus, Shih-Wei Chou
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Patent number: 11764733Abstract: A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.Type: GrantFiled: September 23, 2021Date of Patent: September 19, 2023Assignee: QUALCOMM INCORPORATEDInventors: Shih-Wei Chou, Todd Morgan Rasmus, Ying Duan, Abhay Dixit
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Publication number: 20230143127Abstract: Aspects of the present disclosure provide a method for regulating an integration current of a sensing amplifier. The sensing amplifier includes a first input transistor and a second input transistor, wherein a source of the first input transistor and a source of the second input transistor are coupled to a source node. The method includes pulling a current from or sourcing the current to the source node, measuring the integration current, comparing the measured integration current with a reference signal, and adjusting the current pulled from or sourced to the source node based on the comparison.Type: ApplicationFiled: November 8, 2021Publication date: May 11, 2023Inventors: Todd Morgan RASMUS, Shih-Wei CHOU
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Patent number: 11641294Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.Type: GrantFiled: January 31, 2022Date of Patent: May 2, 2023Assignee: QUALCOMM INCORPORATEDInventors: Chulkyu Lee, Ying Duan, Shih-Wei Chou
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Publication number: 20230087897Abstract: A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Shih-Wei CHOU, Todd Morgan RASMUS, Ying DUAN, Abhay DIXIT
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Patent number: 11585004Abstract: A cobalt electroplating composition may include (a) cobalt ions; and (b) an ammonium compound of formula (NR1R2R3H+)nXn?, wherein R1, R2, R3 are independently H or linear or branched C1 to C6 alkyl, X is one or more n valent inorganic or organic counter ion(s), and n is an integer from 1, 2, or 3.Type: GrantFiled: April 5, 2019Date of Patent: February 21, 2023Assignee: BASF SEInventors: Marco Arnold, Chiao Chien Wei, Tzu Tsang Huang, Shih Ming Lin, Cheng Chen Kuo, Shih Wei Chou, Chieh Chu
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Patent number: 11528995Abstract: A balancing pressure bearing apparatus including a connecting base and bearing components is provided. Inside the connecting base is any material selected from a volume-incompressibe fluid, semifluid and elastic element, and arranged thereabove is each bearing component. The bearing components have bearing surfaces for supporting any pressing-down human body part and pressure reduction. When the connecting base is pressed down, a Pascal phenomenon is generated for a pressure applied to the fluid, semifluid or elastic element inside the connecting base to be transmitted equally in all directions. Each portion thereof has the same pressure for balancing pressure of the supportive bearing surfaces pressed by any two human body parts, thereby reducing and balancing pressures thereon to achieve a more comfortable contact sensation of pressure release and a correct posture effect. Hence, the invention can serve as a cushion, seat, backrest, mattress or pillow product.Type: GrantFiled: April 9, 2021Date of Patent: December 20, 2022Assignee: Great Show Global Co., Ltd.Inventor: Shih-Wei Chou
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Publication number: 20220312975Abstract: A balancing pressure bearing apparatus including a connecting base and bearing components is provided. Inside the connecting base is any material selected from a volume-incompressibe fluid, semifluid and elastic element, and arranged thereabove is each bearing component. The bearing components have bearing surfaces for supporting any pressing-down human body part and pressure reduction. When the connecting base is pressed down, a Pascal phenomenon is generated for a pressure applied to the fluid, semifluid or elastic element inside the connecting base to be transmitted equally in all directions. Each portion thereof has the same pressure for balancing pressure of the supportive bearing surfaces pressed by any two human body parts, thereby reducing and balancing pressures thereon to achieve a more comfortable contact sensation of pressure release and a correct posture effect. Hence, the invention can serve as a cushion, seat, backrest, mattress or pillow product.Type: ApplicationFiled: April 9, 2021Publication date: October 6, 2022Applicant: Great Show Global Co., Ltd.Inventor: Shih-Wei Chou
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Patent number: 11411711Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.Type: GrantFiled: July 9, 2021Date of Patent: August 9, 2022Assignee: QUALCOMM INCORPORATEDInventors: Ying Duan, Jing Wu, Shih-Wei Chou
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Publication number: 20220158879Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Chulkyu LEE, Ying DUAN, Shih-Wei CHOU
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Patent number: 11327914Abstract: Methods, apparatus, and systems for clock and data recovery in a C-PHY interface are disclosed. A receiving device has a plurality of differential receivers and a recovery circuit. The differential receivers are configured to generate difference signals. Each difference signal is representative of voltage difference between one pair of wires in a three-wire serial bus. The recovery circuit is configured to identify a first difference signal that has the greatest voltage magnitude among the plurality of difference signals in a first unit interval and determine signaling state of the three-wire serial bus for the first unit interval based on identity of the pair of wires corresponding to the first difference signal and polarity of the first difference signal in the first unit interval, and to generate a first edge in a clock signal responsive to a transition in the first difference signal during the first unit interval.Type: GrantFiled: January 29, 2021Date of Patent: May 10, 2022Assignee: QUALCOMM INCORPORATEDInventors: Da Ying, Shih-Wei Chou, Ying Duan, Abhay Dixit
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Patent number: 11240077Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.Type: GrantFiled: October 14, 2020Date of Patent: February 1, 2022Assignee: QUALCOMM INCORPORATEDInventors: Chulkyu Lee, Ying Duan, Shih-Wei Chou
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Publication number: 20210336760Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.Type: ApplicationFiled: July 9, 2021Publication date: October 28, 2021Inventors: Ying DUAN, Jing WU, Shih-Wei CHOU
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Patent number: 11116319Abstract: A seat has a base, two seat cushions disposed above the base, and two supporting members mounted on the seat cushions and connected to the base. Each one of the supporting members has multiple supporting elements. Each one of the supporting elements has a guiding rod and a spring. The guiding rod is mounted on the base and is screwed into a corresponding one of the seat cushions. The spring is disposed around the guiding rod. Two ends of the spring abut against the base and the corresponding one of the two seat cushions. In use, the spring can generate different degrees of compression and provide different degrees of supporting force. Deviation of the spring is limited by the guiding rod to avoid excess of the deviation and ensure sufficient support. The seat has both the support and the cushioning performance to improve sitting comfort.Type: GrantFiled: July 1, 2020Date of Patent: September 14, 2021Assignee: CHIA CHI YA ENTERPRISE CO., LTD.Inventors: Yun-Cheng Hsiao, Shih-Wei Chou
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Patent number: 11106610Abstract: In certain aspects, a device comprises one or more IO inputs; a first receiver coupled to a first supply voltage and the one or more IO inputs, wherein the first receiver comprises thick oxide transistors; and a high-speed circuit comprising: an isolation block coupled to the one or more IO inputs, wherein the isolation block comprises thick oxide transistors; and a second receiver coupled to the isolation block and a second supply voltage, wherein the second receiver comprises thin oxide transistors.Type: GrantFiled: September 13, 2019Date of Patent: August 31, 2021Assignee: QUALCOMM IncorporatedInventors: Ying Duan, Shih-Wei Chou, Mansoor Basha Shaik, Harry Dang, Abhay Dixit
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Patent number: 11095425Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.Type: GrantFiled: August 25, 2020Date of Patent: August 17, 2021Assignee: QUALCOMM INCORPORATEDInventors: Ying Duan, Jing Wu, Shih-Wei Chou
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Publication number: 20210184829Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery apparatus has a plurality of pulse generating circuits, a logic circuit and a delay flipflop. Each pulse generating circuit generates transition pulses in response to transitions in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus. Transitions in the difference signals can occur at boundaries between sequentially-transmitted symbols. The first logic circuit may provide a single pulse in a combination signal at each boundary between pairs of symbols by combining one or more transition pulses. The delay flipflop is configured to respond to each pulse in the combination signal by changing signaling state of a clock signal that is output by the clock recovery apparatus. The symbols may be sequentially transmitted over the three-wire bus in accordance with a C-PHY protocol.Type: ApplicationFiled: December 11, 2019Publication date: June 17, 2021Inventors: Ying DUAN, Abhay DIXIT, Shih-Wei CHOU
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Patent number: 11038666Abstract: Methods, apparatus, and systems for communication over a multi-wire, multiphase interface are disclosed. A clock recovery apparatus has a plurality of pulse generating circuits, a logic circuit and a delay flipflop. Each pulse generating circuit generates transition pulses in response to transitions in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus. Transitions in the difference signals can occur at boundaries between sequentially-transmitted symbols. The first logic circuit may provide a single pulse in a combination signal at each boundary between pairs of symbols by combining one or more transition pulses. The delay flipflop is configured to respond to each pulse in the combination signal by changing signaling state of a clock signal that is output by the clock recovery apparatus. The symbols may be sequentially transmitted over the three-wire bus in accordance with a C-PHY protocol.Type: GrantFiled: December 11, 2019Date of Patent: June 15, 2021Assignee: QUALCOMM INCORPORATEDInventors: Ying Duan, Abhay Dixit, Shih-Wei Chou