Patents by Inventor Shih-Wei Chou

Shih-Wei Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6652726
    Abstract: A method for reducing or avoiding semiconductor wafer peripheral defects and contamination during and following electrodeposition including providing a wafer chuck assembly sealably attached to a back side of a semiconductor wafer leaving an exposed peripheral portion of the back side of the semiconductor wafer the backside parallel to a front side of the semiconductor wafer comprising a process surface; contacting at least the semiconductor process surface with a process solution; and, simultaneously directing a pressurized flow of gas onto the exposed peripheral portion such that the pressurized flow of gas covers the exposed peripheral portion including being radially directed outward toward the periphery of the semiconductor wafer.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: November 25, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventor: Shih-Wei Chou
  • Publication number: 20030213697
    Abstract: A method for reducing or avoiding semiconductor wafer peripheral defects and contamination during and following electrodeposition including providing a wafer chuck assembly sealably attached to a back side of a semiconductor wafer leaving an exposed peripheral portion of the back side of the semiconductor wafer the backside parallel to a front side of the semiconductor wafer comprising a process surface; contacting at least the semiconductor process surface with a process solution; and, simultaneously directing a pressurized flow of gas onto the exposed peripheral portion such that the pressurized flow of gas covers the exposed peripheral portion including being radially directed outward toward the periphery of the semiconductor wafer.
    Type: Application
    Filed: May 16, 2002
    Publication date: November 20, 2003
    Applicant: Taiwain Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Wei Chou
  • Patent number: 6649513
    Abstract: A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least a portion of the structure. A first-metal layer is formed over the patterned dielectric layer filling the opening. The first-metal layer including at least a doped metal portion adjacent the patterned dielectric layer. The doped metal portion being doped with a second-metal. The structure is annealed to form a second-metal oxide layer adjacent the patterned dielectric layer. The first-metal layer and the second-metal oxide layer are planarized using only a electropolishing process to remove the excess of the first-metal layer and the second-metal oxide layer from over the patterned dielectric layer and leaving a planarized metal structure within the opening.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: November 18, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ming-Hsing Tsai, Shih-Wei Chou, Winston Shue, Mong-Song Liang
  • Publication number: 20030209444
    Abstract: A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carrying out the electrodeposition process; carrying out the electrodeposition process to electrodeposit a metal onto an electrodeposition surface of the second electrode assembly; and, applying a second current density having a second polarity reversed with reference to the first polarity across the first electrode assembly and the second electrode assembly the second current density having a relatively lower current density compared to the first current density.
    Type: Application
    Filed: May 8, 2002
    Publication date: November 13, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Wen Su, Shih-Wei Chou, Ching-Hua Hsieh, Shau-Lin Shue
  • Publication number: 20030205477
    Abstract: An electrode assembly arrangement for improving an electrodeposition process and method for using the same the electrode assembly arrangement including a first electrode assembly and a second electrode assembly positioned to carry a metal containing electrolyte from the first electrode assembly to the second electrode assembly for deposition of the metal upon applying an electrical potential therebetween; at least one additional electrode assembly including a means for selectively applying an electrical potential thereto the at least one additional electrode assembly positioned to attract an electrolyte flow upon applying an electrical potential between the at least one additional electrode assembly and the second electrode assembly.
    Type: Application
    Filed: May 6, 2002
    Publication date: November 6, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai
  • Publication number: 20030183530
    Abstract: A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.
    Type: Application
    Filed: March 26, 2002
    Publication date: October 2, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai, Winston Shue, Mong-Song Liang
  • Publication number: 20030168345
    Abstract: A method and apparatus for monitoring copper seed layer growth during copper plating of a semiconductor wafer. A ring contact for use in copper plating of the semiconductor wafer is generally divided into a plurality of switches thereof. The ring contact is biased to prior to copper plating of the semiconductor wafer to determine a copper seed layer conductivity. Each switch among the plurality of switches can be connected together and thereafter the switches may be biased to an anode during copper plating, thereby permitting in-situ monitoring of copper seed resistance prior to the copper plating and a detection of copper seed damage and copper seed corrosion associated with the copper plating.
    Type: Application
    Filed: March 7, 2002
    Publication date: September 11, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Minghsing Tsai, Shih-Wei Chou
  • Publication number: 20020143910
    Abstract: A network hub is adapted for controlling connection between a server and multiple work stations in a local-area network. The network hub includes a rectifying and voltage-regulating circuit for outputting a power signal, a signal processing circuit coupled electrically to the rectifying and voltage-regulating circuit for receiving the power signal therefrom, and an output port module coupled electrically to the signal processing circuit. The signal processing circuit receives a command transmitted via an input port module connected to the server, and is operable so as to output control signals corresponding to the command from the server. The output port module has connecting ports coupled electrically to switching circuits, respectively. Each connecting port is connected to a corresponding one of the work stations via network lines. Each control signal is received by a respective one of the switching circuits so as to control conduction or cut-off thereof.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 3, 2002
    Inventors: Shih-Wei Chou, Chih-Wen Wang, Hung-I Tsai