Patents by Inventor Shih-Wei Chou
Shih-Wei Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11023409Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. An apparatus includes a physical layer interface coupled to a serial bus and configurable for a high-speed mode of communication and a low-speed mode of communication, and a rate detector configured to receive a clock signal from the serial bus, and to use a reference clock to determine a unit interval representative of a data rate of the serial bus. The apparatus may also include interval calculation logic configured to determine an interval related to timing of a data signal transmitted on the serial bus, the interval having a duration expressed as a number of cycles of the reference clock. The physical layer interface may be configured to use the interval to capture data in the data signal.Type: GrantFiled: October 3, 2019Date of Patent: June 1, 2021Assignee: QUALCOMM IncorporatedInventors: Yasser Ahmed, Ying Duan, Shih-Wei Chou
-
Publication number: 20210147994Abstract: A cobalt electroplating composition may include (a) cobalt ions; and (b) an ammonium compound of formula (NR1R2R3H+)nX1?, wherein R1, R2, R3 are independently H or linear or branched C1 to C6 alkyl, X is one or more n valent inorganic or organic counter ion(s), and n is an integer from 1, 2, or 3.Type: ApplicationFiled: April 5, 2019Publication date: May 20, 2021Applicant: BASF SEInventors: Marco ARNOLD, Chiao Chien WEI, Tzu Tsang HUANG, Shih Ming LIN, Cheng Chen KUO, Shih Wei CHOU, Chieh CHU
-
Publication number: 20210126819Abstract: Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.Type: ApplicationFiled: October 14, 2020Publication date: April 29, 2021Inventors: Chulkyu LEE, Ying DUAN, Shih-Wei CHOU
-
Publication number: 20210126765Abstract: Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.Type: ApplicationFiled: August 25, 2020Publication date: April 29, 2021Inventors: Ying DUAN, Jing WU, Shih-Wei CHOU
-
Publication number: 20210103547Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. An apparatus includes a physical layer interface coupled to a serial bus and configurable for a high-speed mode of communication and a low-speed mode of communication, and a rate detector configured to receive a clock signal from the serial bus, and to use a reference clock to determine a unit interval representative of a data rate of the serial bus. The apparatus may also include interval calculation logic configured to determine an interval related to timing of a data signal transmitted on the serial bus, the interval having a duration expressed as a number of cycles of the reference clock. The physical layer interface may be configured to use the interval to capture data in the data signal.Type: ApplicationFiled: October 3, 2019Publication date: April 8, 2021Inventors: Yasser AHMED, Ying DUAN, Shih-Wei CHOU
-
Publication number: 20210081339Abstract: In certain aspects, a device comprises one or more IO inputs; a first receiver coupled to a first supply voltage and the one or more IO inputs, wherein the first receiver comprises thick oxide transistors; and a high-speed circuit comprising: an isolation block coupled to the one or more IO inputs, wherein the isolation block comprises thick oxide transistors; and a second receiver coupled to the isolation block and a second supply voltage, wherein the second receiver comprises thin oxide transistors.Type: ApplicationFiled: September 13, 2019Publication date: March 18, 2021Inventors: Ying DUAN, Shih-Wei CHOU, Mansoor Basha SHAIK, Harry DANG, Abhay DIXIT
-
Patent number: 10833899Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.Type: GrantFiled: July 30, 2019Date of Patent: November 10, 2020Assignee: QUALCOMM IncorporatedInventors: Shih-Wei Chou, Chulkyu Lee, Dhaval Sejpal
-
Patent number: 10615785Abstract: Duty cycle correction circuits are provided that include a serial combination of a first inverter and a second inverter for inverting an input clock signal into an output clock signal having a corrected duty cycle. The duty cycle correction circuits also include a serial combination of a third inverter and a fourth inverter for inverting a complement input clock signal into a complement output clock signal having a corrected duty cycle.Type: GrantFiled: March 21, 2019Date of Patent: April 7, 2020Assignee: QUALCOMM IncorporatedInventors: Shih-Wei Chou, Ying Duan, Abhay Dixit, Harry Huy Dang, Thomas Clark Bryan
-
Publication number: 20190356519Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.Type: ApplicationFiled: July 30, 2019Publication date: November 21, 2019Inventors: Shih-Wei CHOU, Chulkyu LEE, Dhaval SEJPAL
-
Patent number: 10419252Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.Type: GrantFiled: July 31, 2018Date of Patent: September 17, 2019Assignee: QUALCOMM IncorporatedInventors: Shih-Wei Chou, Chulkyu Lee, Dhaval Sejpal
-
Patent number: 10419246Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of calibration includes configuring a 3-phase signal to include a high frequency component and a low frequency component during a calibration period, and transmitting a version of the 3-phase signal on each wire of a 3-wire interface. The version of the 3-phase signal transmitted on each wire is out-of-phase with the versions of the 3-phase signal transmitted on each of the other wires of the 3-wire interface. The 3-phase signal may be configured to enable a receiver to determine certain operating parameters of the 3-wire interface.Type: GrantFiled: August 18, 2017Date of Patent: September 17, 2019Assignee: QUALCOMM IncorporatedInventors: Ying Duan, Abhay Dixit, Shih-Wei Chou, Jing Wu, Harry Dang
-
Patent number: 10389315Abstract: A receiver amplifier and also a receiver equalizer is provided for a three-level signaling system. The receiver amplifier includes a single current source that drives a current into node shared by three transistors arranged in parallel. A trio of input signals corresponds to the three transistors on a one-to-one basis. Each input signal drives the gate of its corresponding transistor. In addition, each transistor produces a corresponding output voltage at a terminal coupled to a resistor. The receiver equalizer includes three transistors and three corresponding equalizing pairs of a resistor and a capacitor. A terminal for the capacitor and for the resistor in each equalizing pair connects to a terminal of the corresponding transistor.Type: GrantFiled: March 5, 2018Date of Patent: August 20, 2019Assignee: QUALCOMM IncorporatedInventors: Chulkyu Lee, Shih-Wei Chou, Ying Duan
-
Patent number: 10333690Abstract: Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.Type: GrantFiled: May 4, 2018Date of Patent: June 25, 2019Assignee: QUALCOMM IncorporatedInventors: Ying Duan, Abhay Dixit, Shih-Wei Chou, Chulkyu Lee
-
Patent number: 10298381Abstract: Data communication apparatus and methods for a multi-wire interface are disclosed. A half rate clock and data recovery (CDR) circuit derives a clock signal including pulses corresponding to symbols transmitted on a 3-wire interface, where the symbols are transmitted at a particular frequency with each of the symbols occurring over a unit interval (UI) time period. The first clock signal is input to a flip-flop logic included in a delay loop, and serves to trigger the first flip-flop logic. A second clock signal is generated using a programmable generator in the delay loop and has a frequency of a half UI and is fed back to a data input of the flip-flop. The output of the flip-flop is used as a recovered clock signal for the CDR at a half rate frequency. This design provides ease of timing control, a delay line without extra nonlinear-effects, and less hardware overhead.Type: GrantFiled: April 30, 2018Date of Patent: May 21, 2019Assignee: QUALCOMM IncorporatedInventors: Chulkyu Lee, Shih-Wei Chou, Ying Duan
-
Patent number: 10289600Abstract: A method for error detection in transmissions on a multi-wire interface includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.Type: GrantFiled: October 24, 2016Date of Patent: May 14, 2019Assignee: QUALCOMM IncorporatedInventors: Dhaval Sejpal, Shih-Wei Chou, Chulkyu Lee, Ohjoon Kwon, George Alan Wiley
-
Publication number: 20180358939Abstract: A receiver amplifier and also a receiver equalizer is provided for a three-level signaling system. The receiver amplifier includes a single current source that drives a current into node shared by three transistors arranged in parallel. A trio of input signals corresponds to the three transistors on a one-to-one basis. Each input signal drives the gate of its corresponding transistor. In addition, each transistor produces a corresponding output voltage at a terminal coupled to a resistor. The receiver equalizer includes three transistors and three corresponding equalizing pairs of a resistor and a capacitor.Type: ApplicationFiled: March 5, 2018Publication date: December 13, 2018Inventors: Chulkyu Lee, Shih-Wei Chou, Ying Duan
-
Publication number: 20180337698Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.Type: ApplicationFiled: July 31, 2018Publication date: November 22, 2018Inventors: Shih-Wei CHOU, Chulkyu LEE, Dhaval SEJPAL
-
Publication number: 20180234122Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level. The dedicated transistor is activated based on a voltage level for driving a second terminal of the three terminals and a voltage level for driving a third terminal of the three terminals.Type: ApplicationFiled: April 11, 2018Publication date: August 16, 2018Inventors: Shih-Wei Chou, Chulkyu Lee, Dhaval Sejpal
-
Patent number: 9998154Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level. The dedicated transistor is activated based on a voltage level for driving a second terminal of the three terminals and a voltage level for driving a third terminal of the three terminals.Type: GrantFiled: June 3, 2016Date of Patent: June 12, 2018Assignee: QUALCOMM IncorporatedInventors: Shih-Wei Chou, Chulkyu Lee, Dhaval Sejpal
-
Patent number: 9978681Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer includes metal ions.Type: GrantFiled: August 27, 2015Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Hung-Wen Su, Shih-Wei Chou, Ming-Hsing Tsai