Abstract: A semiconductor structure includes: a buried power rail disposed between a first fin structure and a second fin structure on a substrate extending in a first direction in a horizontal plane, the first fin structure located in a first cell, the second fin structure located in a second cell abutting the first cell at a boundary line extending in the first direction, the buried power rail providing a first voltage; and a metal one (M1) metal track disposed in a M1 layer extending in a second direction in the horizontal plane. At an intersection of the buried power rail and the M1 metal track, the semiconductor structure further includes an electrically conductive path to provide the first voltage to the M1 metal track, the electrically conductive path having a first metal zero (M0) metal track extending in the first direction over the boundary line.

Abstract: In one embodiment, an integrated circuit includes a first pattern metal layer, a second pattern metal layer formed over the first pattern metal layer, wherein the second pattern metal layer comprises a second plurality of metal tracks extending in a first direction and less than 9, a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including, a first metal track segment, a second metal track segment shifted in a second direction from the first metal track segment, and a third metal track segment shifted in the second direction from the second metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment, the second metal track segment, and the third metal track segment are within a double cell height in the second direction.

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Abstract: An integrated circuit includes a first buried power rail, a second buried power rail, a first power pad in a first metal layer, and a first conductive segment beneath the first metal layer. The first buried power rail and the second buried power rail are both located beneath the first metal layer. The first power pad is configured to receive a first supply voltage through at least one first via. The first conductive segment is conductively connected to the first power pad through at least one second via between the first conductive segment and the first metal layer. The first conductive segment is conductively connected to the first buried power rail through at least one third via between the first conductive segment and the first buried power rail.

Abstract: An IC device includes a gate structure including an isolation layer laterally adjacent to a gate electrode, a transistor including a first S/D structure, a second S/D structure, and a channel extending through the gate electrode, a third S/D structure overlying the first S/D structure, a fourth S/D structure overlying the second S/D structure, and a conductive structure overlying the isolation layer and configured to electrically connect the third S/D structure to the fourth S/D structure.

Abstract: Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.

Abstract: A device includes a first transistor, a second transistor, and a contact. The first transistor includes a first source/drain, a second source/drain, and a first gate between the first and second source/drains. The second transistor includes a third source/drain, a fourth source/drain, and a second gate between the third and fourth source/drains. The contact covers the first source/drain of the first transistor and the third source/drain of the third transistor. The first contact is electrically connected to the first source/drain of the first transistor and electrically isolated from the third source/drain of the third transistor.

Abstract: A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules.

Abstract: An IC structure includes a first plurality of metal segments extending in a first metal layer in a first direction and having a first pitch in a second direction perpendicular to the first direction, a second plurality of metal segments extending in a second metal layer in the second direction and having a second pitch in the first direction, and a third plurality of metal segments extending in a third metal layer in the first direction and having a third pitch in the second direction. The second metal layer is a next consecutive layer overlying the first metal layer, the third metal layer is a next consecutive layer overlying the second metal layer, and a ratio of the second pitch to the third pitch is greater than one.

Abstract: A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell that are arranged in a first direction; forming a plurality of first metal strips extending in the first direction and arranged in a second direction on a first plane; forming a first trench over a boundary between the first cell and the second cell, wherein a bottom surface of the first trench is on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall which extends in the first direction; and forming a plurality of second metal strips extending in the second direction on a third plane over the second plane, wherein a first second metal strip and a second second metal strip separated from each other by the separating wall; wherein the second direction is orthogonal to the first direction.

Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

Abstract: A method generating a layout diagram includes: arranging the layout diagram into rows; configuring one or more of the rows as combination rows, the combination-row-configuring including relative to a second direction substantially perpendicular to the first direction, setting a height of each of the one or more combination rows to be substantially equal to a sum of a first height of a first cell and a second height of a second cell, the first cell being different than the second cell, and the first height being different than the second height; and populating each of the one or more combination rows including: stacking a first instance of the first cell on a first instance of the second cell, or stacking a second instance of the second cell on a second instance of the first cell.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes arranging first conductive feature layout patterns in a cell region. The first conductive feature layout patterns extend in a first direction, and the cell region has opposite first and second cell boundaries extending in a second direction. Second conductive feature layout patterns are arranged in the cell region and extending in the first direction. The first and second conductive feature layout patterns are alternately arranged. First cut feature layout patterns are arranged on the first cell boundary of the cell region and on ends of the first conductive feature layout patterns. One of the first cut feature layout patterns is offset from another one of the first cut feature layout patterns in the first direction. The IC layout diagram including the first and second conductive feature layout patterns and the first cut feature layout patterns is generated.

Abstract: A structure includes a first transistor of a first type, the first transistor including a first channel, a first conductive segment, and a second conductive segment, a second transistor of a second type, the second transistor including a second channel, a third conductive segment, and a fourth conductive segment, and a gate. The first channel extends through the gate between the first and second conductive segments, the second channel extends through the gate between the third and fourth conductive segments and is aligned with the first channel at a center of the first transistor, the first and third conductive segments extend away from the center of the first transistor in opposite directions, and the second and fourth conductive segments extend away from the center of the first transistor in opposite directions.

Abstract: A semiconductor device includes a dielectric layer having a first surface and a second surface opposite to the first surface; an active region on the first surface of the dielectric layer; a power rail under the second surface of the dielectric layer, wherein the dielectric layer is between the active region and the power rail; a spacer physically dividing the active region into a first part and a second part, the first part and the second part being conductively isolated from each other by the spacer; an intermediate layer comprising: first and second conductive segments; and wherein the spacer joins the first conductive segment and the second conductive segment, and electrically isolates the first conductive segment from the second conductive segment, wherein a join length between the first conductive segment and the spacer is equal to a join length between the second conductive segment and the spacer.

Abstract: An integrated circuit includes two buried power rails located beneath a first metal layer overlying the substrate, and two upper power rails in a second metal layer overlying the first metal layer. The two upper power rails are perpendicular to the two buried power rails. The integrated circuit includes a power pick-up cell having a functional circuit. The functional circuit includes a conductive segment beneath the first metal layer and a power pad in the first metal layer. The power pad is conductively connected to one of the upper power rails through a first via. The first power pad is conductively connected to the first conductive segment through a second via. The first conductive segment is conductively connected to one of the buried power rails through a third via.

Abstract: A method (of generating a layout diagram) includes: for a first cell which includes first and second active area patterns, a cell-boundary (CB) having first and second edge portions (EPs) substantially parallel to a vertical direction (VEPs), and first and second VEP-adjacent regions correspondingly adjacent the first and second VEPs: configuring the first VEP-adjacent region (VAR) to be a first active area (AA) continuous (AA-continuous) region in which the first active area pattern extends in a horizontal direction from an interior of the first cell to the first VEP; and configuring the second VAR to be a first AA-discontinuous region, the second active area pattern extending in the horizontal direction from the interior of the first cell towards the second VEP, and there being a first gap between a first end of the second active area pattern and the second VEP representing the first AA-discontinuous region.

Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin.

Abstract: A semiconductor device, including: a substrate, a transistor layer, a dielectric layer, and a power grid structure. The transistor layer is formed on a first side of the substrate and includes a plurality of active regions for forming transistors. The dielectric layer is formed on the transistor layer and includes a conductive strip disposed on a first active region and extending toward a second active region for signal connection. The power grid structure is formed on a second side of the substrate opposite to the first side and arranged to direct a power source to the transistor layer.