Abstract: Disclosed embodiments herein relate to an integrated circuit including metal rails. In one aspect, the integrated circuit includes a first layer including a first metal rail and a second layer including a second metal rail, where the second layer is above the first layer along a first direction. In one aspect, the integrated circuit includes a third layer including an active region of a transistor, where the third layer is above the second layer along the first direction. In one aspect, the integrated circuit includes a fourth layer including a third metal rail, where the fourth layer is above the third layer along the first direction. In one aspect, the integrated circuit includes a fifth layer including a fourth metal rail, where the fifth layer is above the fourth layer along the first direction.

Abstract: An integrated circuit includes a semiconductor substrate, transistors on the semiconductor, horizontal routing tracks extending in a first direction in a first metal layer, and one or more backside routing tracks extending in the first direction in a backside metal layer. Each transistor has a gate terminal, a source terminal, and a drain terminal. A first transistor has a first terminal, a second terminal, and a third terminal. A first horizontal routing track of the horizontal routing tracks is conductively connected to the first terminal of the first transistor through a via connector. A first backside routing track is conductively connected to the second terminal of the first transistor through a backside via connector. The backside metal layer and the first metal layer are formed at opposite sides of the semiconductor substrate.

Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including a first level of metallization (M_1st level) and a first level of interconnection (VIA_1st level) thereover corresponding to a first layer of metallization and a first layer of interconnection thereover in the semiconductor device, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and increasing a size of the candidate pattern thereby revising the layout diagram.

Abstract: A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell, the first cell and the second. cell are arranged in a first direction; forming a plurality of first metal strips arranged in a second direction and extending in the first direction on a first plane; forming a first trench over a boundary between the first cell and the second cell, a bottom surface of the first trench is located on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall extending in the first direction; and fort plurality of second metal strips extending in the second direction on a third plane over the second plane and including a first second metal strip and a second second metal strip separated by the separating wall.

Abstract: A device includes a first transistor, a second transistor, and a contact. The first transistor includes a first source/drain, a second source/drain, and a first gate between the first and second source/drains. The second transistor includes a third source/drain, a fourth source/drain, and a second gate between the third and fourth source/drains. The contact covers the first source/drain of the first transistor and the third source/drain of the second transistor. The contact is electrically connected to the first source/drain of the first transistor and electrically isolated from the third source/drain of the second transistor.

Abstract: An integrated circuit includes a set of power rails, a set of active regions, a first set of conductive lines and a first and a second set of vias. The set of power rails is configured to supply a first or second supply voltage, and is on a first level of a back-side of a substrate. The set of active regions is a second level of a front-side of the substrate. The first set of conductive lines extend in a second direction and overlap the set of active regions. The first set of vias is between and electrically couples the set of active regions and the first set of conductive lines together. The second set of vias is between and electrically couples the first set of conductive lines and the set of power rails together.

Abstract: A semiconductor device includes a first transistor of a first conductivity type and a second transistor of a second conductivity type. The first transistor is arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device also includes a first conductive line arranged in a third layer between the first layer and the second layer and extending in the second direction, wherein the first conductive line is configured to electrically connect a first source/drain region of the first active region to a second source/drain region of the second active region.

Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

Abstract: A layout method includes: generating a design data including an electronic circuit; and generating a design layout by placing a cell corresponding to the electronic circuit. The cell includes a first transistor and a second transistor over the first transistor. The first transistor includes a gate extending in a first direction, a first active region arranged in a first layer and extending in a second direction, and a first conductive line and a second conductive line arranged on two sides of the first active region. The second transistor includes the gate, a second active region arranged in a second layer over the first layer and extending in the second direction, and a third conductive line and a fourth conductive line arranged on two sides of the second active region. At least one of the four conductive lines includes a first portion non-overlapped with the gate in the first direction.

Abstract: A semiconductor device, including: a substrate, a transistor layer, a dielectric layer, and a power grid structure. The transistor layer is formed on a first side of the substrate and includes a plurality of active regions for forming transistors. The dielectric layer is formed on the transistor layer and includes a conductive strip disposed on a first active region and extending toward a second active region for signal connection. The power grid structure is formed on a second side of the substrate opposite to the first side and arranged to direct a power source to the transistor layer.

Abstract: An integrated circuit includes a first, second and third active region and a first, second and third conductive line. The first, second and third active regions extend in a first direction, and are on a first level of a front-side of a substrate. The second active region is between the first active region and the third active region. The first and second conductive line extend in the first direction, and are on a second level of a back-side of the substrate. The first conductive line is between the first and second active region. The second conductive line is between the second and third active region. The third conductive line extends in the second direction, is on a third level of the back-side of the substrate, overlaps the first and second conductive line, and electrically couples the first and second active regions.

Abstract: An integrated circuit cell is provided, which may include a substrate with a front side and a back side, an active region, a first via, and first, second and third conductive layers. A portion of the active region may be formed within the substrate. The first via and the first, second and third conductive layers are on the back side. The second and third conductive layers may be located further away from the substrate in a first direction than the first and second conductive layers, respectively. The depth of the first via may be greater than a distance between the second conductive layer and the third conductive layer. The integrated circuit cell may include a cell height in a second direction substantially perpendicular to the first direction. A width of the first via along the second direction may be between about 0.05 to about 0.25 times the cell height.

Abstract: A flap for a cage for holding electronic devices in a computing system is disclosed. The flap includes a main segment, a first vertical extension, a second vertical extension, a lateral ledge, and a tapered ledge. The first vertical extension and the second vertical extension extend from a first side of the main segment. The lateral ledge extends from a third side of the main segment. The tapered extensions extend from a second side of the main segment and include a flat section and an angled section. The flap has a deployed position and a stored position in the cage. The flap engages with at least two sides of the cage in the deployed or the stored position. The flap may be in the stored position when an electronic component is present. The flap blocks airflow through the cage in the deployed position.

Abstract: Disclosed embodiments herein relate to an integrated circuit including metal rails. In one aspect, the integrated circuit includes a first layer including a first metal rail and a second layer including a second metal rail, where the second layer is above the first layer along a first direction. In one aspect, the integrated circuit includes a third layer including an active region of a transistor, where the third layer is above the second layer along the first direction. In one aspect, the integrated circuit includes a fourth layer including a third metal rail, where the fourth layer is above the third layer along the first direction. In one aspect, the integrated circuit includes a fifth layer including a fourth metal rail, where the fifth layer is above the fourth layer along the first direction.

Abstract: An integrated circuit is disclosed. The integrated circuit includes conductive rails, signal rails, at least one first via, and at least one first conductive segment. The at least one first via is disposed between the first conductive layer and the second conductive layer, and couples a first signal rail of the signal rails to at least one of the conductive rails. The first signal rail is configured to transmit a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first conductive segment is disposed between the first conductive layer and the second conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.

Abstract: A flap for a cage for holding electronic devices in a computing system is disclosed. The flap includes a main segment, a first vertical extension, a second vertical extension, a lateral ledge, and a tapered ledge. The first vertical extension and the second vertical extension extend from a first side of the main segment. The lateral ledge extends from a third side of the main segment. The tapered extensions extend from a second side of the main segment and include a flat section and an angled section. The flap has a deployed position and a stored position in the cage. The flap engages with at least two sides of the cage in the deployed or the stored position. The flap may be in the stored position when an electronic component is present. The flap blocks airflow through the cage in the deployed position.

Abstract: A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell that are arranged in a first direction; forming a plurality of first metal strips extending in the first direction and arranged in a second direction on a first plane; forming a first trench over a boundary between the first cell and the second cell, wherein a bottom surface of the first trench is on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall which extends in the first direction; and forming a plurality of second metal strips extending in the second direction on a third plane over the second plane, wherein a first second metal strip and a second second metal strip separated from each other by the separating wall; wherein the second direction is orthogonal to the first direction.

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: An integrated circuit cell is provided, which may include a substrate with a front side and a back side, an active region, a first via, and first, second and third conductive layers. A portion of the active region may be formed within the substrate. The first via and the first, second and third conductive layers are on the back side. The second and third conductive layers may be located further away from the substrate in a first direction than the first and second conductive layers, respectively. The depth of the first via may be greater than a distance between the second conductive layer and the third conductive layer. The integrated circuit cell may include a cell height in a second direction substantially perpendicular to the first direction. A width of the first via along the second direction may be between about 0.05 to about 0.25 times the cell height.

Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern); determining that the candidate pattern satisfies one or more criteria; and changing a size of the candidate pattern thereby revising the layout diagram.