Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Abstract: Disclosed embodiments herein relate to an integrated circuit including metal rails. In one aspect, the integrated circuit includes a first layer including a first metal rail and a second layer including a second metal rail, where the second layer is above the first layer along a first direction. In one aspect, the integrated circuit includes a third layer including an active region of a transistor, where the third layer is above the second layer along the first direction. In one aspect, the integrated circuit includes a fourth layer including a third metal rail, where the fourth layer is above the third layer along the first direction. In one aspect, the integrated circuit includes a fifth layer including a fourth metal rail, where the fifth layer is above the fourth layer along the first direction.

Abstract: One aspect of this description relates to an integrated circuit. In some aspects, the integrated circuit includes a first pattern metal layer, a second pattern metal layer disposed over the first pattern metal layer, wherein the second pattern metal layer includes a second plurality of metal tracks extending in a first direction, and a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including a first metal track segment and a second metal track segment shifted in a second direction from the first metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment and the second metal track segment are within a double cell height in the second direction.

Abstract: An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.

Abstract: A layout method and a layout system are disclosed. The layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region, a second source/drain region and a gate electrode, wherein the gate electrode define an odd-numbered track and an even-numbered track. The first cell also includes a first power rail, a first conductive via within the odd-numbered track, a second power rail and a second conductive via within the even-numbered track. The first source/drain region is electrically connected to the first power rail through the first conducive via, and the second source/drain region is electrically connected to the second power rail through the second conducive via.

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

Abstract: A method of forming an IC device includes creating a recess by removing at least a portion of a channel of a first transistor and a portion of a gate electrode, the gate electrode being common to the first transistor and an underlying second transistor. The method includes filling the recess with a dielectric material to form an isolation layer, and constructing a slot via overlying the isolation layer.

Abstract: A method of manufacturing a semiconductor device including the operations of defining a first metal pattern (MX-1) having a first metal pattern pitch (MX-1P); depositing an insulating layer over the first metal pattern; defining a core grid having a plurality of core locations having a coreX pitch (CoreXP) on the insulating layer; removing predetermined portions of the insulating layer to form a plurality of core openings through a predetermined set of the core locations; and elongating the core openings using a directional etch (DrE) to form expanded core openings that are used to form the next metal layer MX pattern.

Abstract: An IC package includes a first die including a front side and a back side, the front side including a first signal routing structure, the back side including a first power distribution structure, and a second die including a front side and a back side, the front side including a second signal routing structure, the back side including a second power distribution structure. The IC package includes a third power distribution structure positioned between the first and second power distribution structures and electrically connected to each of the first and second power distribution structures.

Abstract: A method generating the layout diagram includes: selecting gate patterns for which a first distance from a corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each of the selected gate patterns, increasing a size of the corresponding cut-gate section from a first value to a second value; the second value resulting in a first type of overhang of a corresponding remnant portion of the corresponding gate pattern; and the first type of overhang being a minimal permissible amount of overhang of the corresponding remnant portion beyond the corresponding first or second nearest active area pattern. A result is that gaps between ends of corresponding ends of remnants of gate patters are expanded.

Abstract: A semiconductor device includes a cell. The cell includes an active area, gates, at least one gate via and at least one contact via. The active area includes forbidden regions. The gates are disposed across the active area. The at least one gate via is coupled with one of the gates. The at least one contact via is coupled with at least one conductive segment each corresponding to a source/drain of a transistor. In a layout view, one of the forbidden regions abuts a region of an abutted cell in which at least one of a gate via or a contact via of the abutted cell is disposed. In a layout view, the least one of the at least one gate via or the at least one contact via is arranged within the active area and outside of the forbidden regions. A method is also disclosed herein.

Abstract: An integrated circuit includes a strip structure having a front side and a back side. A gate structure is on the front side of the strip structure. The integrated circuit includes a plurality of channel layers above the front side of the strip structure, wherein each of the plurality of channel layers is enclosed within the gate structure. An isolation structure surrounds the strip structure. The integrated circuit includes a backside via in the isolation structure. An epitaxy structure is on the front side of the strip structure. The integrated circuit includes a contact over the epitaxy structure. The contact has a first portion on a first side of the epitaxy structure. The first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and contacting the backside via.

Abstract: A device includes a first cell, a second cell, and first isolation portions. The second cell is adjacent the first cell. The first and second cells are arranged in a first direction, and the first cell includes first and second conductive structures. The first conductive structures extend in the first direction. Each of the first conductive structures has a first end facing the second cell. The second conductive structures extend in the first direction. The first and second conductive structures are alternately arranged in a second direction different from the first direction. The first isolation portions are respectively abutting the first ends of the first conductive structures. Two of the first isolation portions are misaligned with each other in the second direction.

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: An integrated circuit includes a first and a second active region, a first contact, a second contact and a first insulating layer. The first active region is in a substrate, extends in a first direction, and is located on a first level. The second active region is in the substrate, extends in the first direction, is located on the first level, and is separated from the first active region in a second direction. The first contact is coupled to the first and the second active region, extends in the second direction, is located on a second level, and overlaps the first and the second active region. The second contact extends in the second direction, overlaps the first contact, and is located on a third level. The first insulating layer extends in the second direction, and is between the second contact and the first contact.

Abstract: In one embodiment, an integrated circuit includes a first pattern metal layer, a second pattern metal layer formed over the first pattern metal layer, wherein the second pattern metal layer comprises a second plurality of metal tracks extending in a first direction and less than 9, a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including, a first metal track segment, a second metal track segment shifted in a second direction from the first metal track segment, and a third metal track segment shifted in the second direction from the second metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment, the second metal track segment, and the third metal track segment are within a double cell height in the second direction.

Abstract: A semiconductor structure includes: a buried power rail disposed between a first fin structure and a second fin structure on a substrate extending in a first direction in a horizontal plane, the first fin structure located in a first cell, the second fin structure located in a second cell abutting the first cell at a boundary line extending in the first direction, the buried power rail providing a first voltage; and a metal one (M1) metal track disposed in a M1 layer extending in a second direction in the horizontal plane. At an intersection of the buried power rail and the M1 metal track, the semiconductor structure further includes an electrically conductive path to provide the first voltage to the M1 metal track, the electrically conductive path having a first metal zero (M0) metal track extending in the first direction over the boundary line.

Abstract: In one embodiment, an integrated circuit includes a first pattern metal layer, a second pattern metal layer formed over the first pattern metal layer, wherein the second pattern metal layer comprises a second plurality of metal tracks extending in a first direction and less than 9, a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including, a first metal track segment, a second metal track segment shifted in a second direction from the first metal track segment, and a third metal track segment shifted in the second direction from the second metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment, the second metal track segment, and the third metal track segment are within a double cell height in the second direction.

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Abstract: An integrated circuit includes a first buried power rail, a second buried power rail, a first power pad in a first metal layer, and a first conductive segment beneath the first metal layer. The first buried power rail and the second buried power rail are both located beneath the first metal layer. The first power pad is configured to receive a first supply voltage through at least one first via. The first conductive segment is conductively connected to the first power pad through at least one second via between the first conductive segment and the first metal layer. The first conductive segment is conductively connected to the first buried power rail through at least one third via between the first conductive segment and the first buried power rail.