Patents by Inventor Shih-Yuan Wang

Shih-Yuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321288
    Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
  • Patent number: 10798288
    Abstract: A multi-camera electronic device and a control method thereof are proposed. The method includes the following steps. At least one camera of the electronic device is used for scene detection to generate photographing analysis information. All the photographing analysis information is collected, and joint photographing information including a joint target is generated through a communication process among all the cameras. An individual photographing parameter of each camera is generated according to the joint photographing information. Each camera is controlled to capture an image of the scene by using its individual photographing parameter to respectively generate a corresponding output image.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 6, 2020
    Assignee: Altek Semiconductor Corp.
    Inventors: Hong-Long Chou, Shih-Yuan Peng, Hsin-Te Wang, Kai-Yu Tseng, Wen-Yan Chang
  • Patent number: 10763260
    Abstract: A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Ting Ho, Shih-Fang Tzou, Chun-Yuan Wu, Li-Wei Feng, Yu-Chieh Lin, Ying-Chiao Wang, Tsung-Ying Tsai
  • Patent number: 10756266
    Abstract: Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switching layer.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: August 25, 2020
    Assignee: WWRAM DEVICES, INC.
    Inventors: Shih-Yuan Wang, Shih-Ping Wang
  • Publication number: 20200238473
    Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yuan YANG, Huai-Tei YANG, Yu-Chen WEI, Szu-Cheng WANG, Li-Hsiang CHAO, Jen-Chieh LAI, Shih-Ho LIN
  • Patent number: 10700225
    Abstract: Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 30, 2020
    Assignee: W&WSENS DEVICES, INC.
    Inventors: Shih-Yuan Wang, Shih-Ping Wang
  • Patent number: 10692817
    Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
  • Publication number: 20200176574
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Application
    Filed: May 10, 2019
    Publication date: June 4, 2020
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Patent number: 10672969
    Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsien Tsai, Shang-Ying Tsai, Fu-Lung Hsueh, Shih-Ming Yang, Jheng-Yuan Wang, Ming-De Chen
  • Publication number: 20200152521
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20200124967
    Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
  • Patent number: 10622498
    Abstract: Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: April 14, 2020
    Assignee: W&WSENS DEVICES, INC.
    Inventors: Shih-Yuan Wang, Shih-Ping Wang
  • Publication number: 20200101580
    Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.
    Type: Application
    Filed: November 9, 2018
    Publication date: April 2, 2020
    Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu
  • Patent number: 10558120
    Abstract: A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: February 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
  • Patent number: 10543092
    Abstract: A bone implant adapted to be implanted in a bone structure having a bone tissue, a cartilage tissue, and being formed with a hole is provided. The bone implant includes a scaffold disposed in the hole for connecting with the bone tissue, a connecting layer disposed on the scaffold, and a porous surface layer. The connecting layer includes a bottom portion connected to the scaffold and an extension portion extending from the bottom portion and formed with a plurality of receiving chambers. The porous surface layer is connected to the extension portion and includes a plurality of filler portions respectively filling the receiving chambers, and a tissue-connecting portion configured for connecting with the cartilage tissue.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 28, 2020
    Assignee: METAL INDUSTRIES RESEARCH AND DEVELOPMENT CENTRE
    Inventors: Jian-Yuan Huang, Chen-Chie Wang, Shih-Hua Huang
  • Publication number: 20200028000
    Abstract: Lateral and vertical microstructure enhanced photodetectors and avalanche photodetectors are monolithically integrated with CMOS/BiCMOS ASICs and can also be integrated with laser devices using fluidic assembly techniques. Photodetectors can be configured in a vertical PIN arrangement or lateral metal-semiconductor-metal arrangement where electrodes are in an inter-digitated pattern. Microstructures, such as holes and protrusions, can improve quantum efficiency in silicon, germanium and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.
    Type: Application
    Filed: August 1, 2019
    Publication date: January 23, 2020
    Applicant: W&Wsens Devices, Inc.
    Inventors: Shih-Yuan WANG, Shih-Ping WANG
  • Patent number: 10529629
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20200006508
    Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.
    Type: Application
    Filed: March 29, 2019
    Publication date: January 2, 2020
    Inventors: Chun-Yuan LO, Shih-Chen WANG, Wen-Hao CHING, Chih-Hsin CHEN, Wei-Ren CHEN
  • Publication number: 20200006650
    Abstract: Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switching layer.
    Type: Application
    Filed: August 9, 2019
    Publication date: January 2, 2020
    Applicant: W&Wram Devices, Inc.
    Inventors: Shih-Yuan WANG, Shih-Ping WANG
  • Patent number: 10511386
    Abstract: Examples include generating a signal using a modulatable source. The signal may be propagated using a multi-mode fiber to receive the signal from the modulatable source. The fiber has a diameter d and a far-field divergence angle associated with the propagated signal that corresponds to a product of the diameter (d) and the far-field divergence angle. The product may be substantially between 1 micron radian and 4 micron radian. In some examples, the propagated signal may be received at a receiver from the multi-mode fiber.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: December 17, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Wayne V. Sorin, Michael Renne Ty Tan, Shih-Yuan Wang