Abstract: Disclosed is a method for determining a memory stability and a testing coverage. The method includes: providing multiple testing programs, for testing each memory die by using one of the testing programs to generate a failure bit information of each memory die; acquiring the failure bit information of each memory die tested with the each testing program; acquiring a failure bit address information of each memory die tested with each testing program based on the failure bit information of each memory die; acquiring a common failure bit address of the testing programs based on the failure bit address information of each memory die, or acquiring a different failure bit address of each testing program based on the failure bit address information of each memory die; and determining a testing coverage based on the common failure bit address, or determining a testing coverage based on the different failure bit address.

Abstract: A peripheral circuit system of a memory device and a memory device are provided. The peripheral circuit system of a memory device includes a first peripheral circuit electrically connected to a memory array of the memory device, and a second peripheral circuit electrically connected to the memory array. The first peripheral circuit and the second peripheral circuit are arranged along a longitudinal direction.

Abstract: An electronic device includes a housing and two electronic modules. The housing has an accommodation space. The accommodation space has a first cross-sectional shape perpendicular to a first direction. The two electronic modules are disposed in the accommodation space. Each of the electronic modules has a concave-convex surface. The concave-convex surfaces of the two electronic modules are arranged oppositely and cooperate with each other, so that the two electronic modules together form a second cross-sectional shape perpendicular to the first direction, and the second cross-sectional shape matches the first cross-sectional shape.

Abstract: Disclosed is a method for determining a memory stability and a testing coverage. The method includes: providing multiple testing programs, for testing each memory die by using one of the testing programs to generate a failure bit information of each memory die; acquiring the failure bit information of each memory die tested with the each testing program; acquiring a failure bit address information of each memory die tested with each testing program based on the failure bit information of each memory die; acquiring a common failure bit address of the testing programs based on the failure bit address information of each memory die, or acquiring a different failure bit address of each testing program based on the failure bit address information of each memory die; and determining a testing coverage based on the common failure bit address, or determining a testing coverage based on the different failure bit address.

Abstract: In an aspect there is provided a semiconductor device including: first and second parallel multilayered active regions, each including at least one lower semiconductor layer and at least one upper semiconductor layer stacked over the at least one lower semiconductor layer; and a PIN diode structure including: an epitaxial first lower semiconductor body arranged along a first portion of the first active region, at a level of the at least one lower semiconductor layer of the first active region, and an epitaxial second lower semiconductor body arranged along a second portion of the second active region directly opposite to the first portion, at a level of the at least one lower semiconductor layer of the second active region; an epitaxial first upper semiconductor body arranged along the first portion, at a level of the at least one upper semiconductor layer of the first active region and spaced apart from the first lower semiconductor body, and an epitaxial second upper semiconductor body arranged along the se

Abstract: The application discloses a neural network system, a method, and a device for processing floating-point number. A self-defined floating-point number is obtained, wherein the self-defined floating-point number comprises a sign field, an exponent field, and a mantissa field, and a value of the self-defined floating-point number is determined by bit of the sign field, bits of the exponent field, bits of the mantissa field, and a bias value, wherein the bias value is determined by a total bit number of the exponent field. The self-defined floating-point number is applied to numerical calculations.

Abstract: The application discloses a processing method and device for floating-point numbers, a neural network (NN) training method, and a floating-point number database conversion method. A custom floating-point number is acquired, wherein the custom floating-point number includes a sign field and an exponent field, and a numerical value of the custom floating-point number is determined by the sign field, the exponent field, a base value, and a bias value, where the base value is a non-integer value greater than 1 and less than 2. The custom floating-point number is applied in numerical calculations.

Abstract: A chassis includes a fixing base, an operating member, a tray and a cover. The operating member is pivotally connected to the fixing base. The operating member includes a first linkage portion. The tray is disposed on the fixing base. The tray includes a second linkage portion corresponding to the first linkage portion. The cover is disposed on the fixing base and covers the tray. When the operating member is located at a closed position, the operating member and the fixing base are locked, and the first linkage portion blocks the second linkage portion, so as to fix the tray on the fixing base. When the operating member rotates from the closed position to an opened position, the first linkage portion pushes the second linkage portion to drive the tray to move toward outside of the fixing base.

Abstract: Disclosed are a method and an apparatus for memory testing. The method comprises following steps: using a test program group including N test programs to test M dies respectively to generate independent N test data, wherein N and M are positive integers greater than 1; and executing a neural network operation on the N test data to estimate a yield of M dies passing the test program group.

Abstract: A memory device for artificial intelligence calculation includes a memory structure, a controller chip, and a processer chip. The memory structure includes a first memory chip, and a stack of second memory chips, in which a memory density of each of the second memory chips is greater than a memory density of the first memory chip. The controller chip is electrically connected to the first memory chip and the second memory chips. The processer chip is electrically connected to the controller chip.

Abstract: A memory device includes a peripheral substrate and an array substrate. The peripheral substrate includes a page buffer and a high voltage processing circuits and has a peripheral substrate area. The array substrate includes an array. The array substrate and the peripheral substrate are stacked on each other, and a circuit distribution area of the high voltage processing circuit accounts for less than 10% of the peripheral substrate area.

Abstract: Disclosed are a method and an apparatus for memory testing. The method comprises following steps: using a test program group including N test programs to test M dies respectively to generate independent N test data, wherein N and M are positive integers greater than 1; and executing a neural network operation on the N test data to estimate a yield of M dies passing the test program group.

Abstract: A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

Abstract: A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

Abstract: A server includes a chassis and a storage module. The storage module is disposed in the chassis. The storage module includes a base, a first electrical connector, a storage device, a connecting member and a first fixing member. A first side of the base has a first fixing portion. The first electrical connector is disposed at a second side of the base, wherein the second side is opposite to the first side. The storage device has a second electrical connector. The connecting member is connected to the storage device. The first fixing member is disposed on the connecting member. The second electrical connector is connected to the first electrical connector and the first fixing member is fixed to the first fixing portion, so as to fix the storage device on the base.

Abstract: A server includes a chassis and a storage module. The storage module is disposed in the chassis. The storage module includes a base, a first electrical connector, a storage device, a connecting member and a first fixing member. A first side of the base has a first fixing portion. The first electrical connector is disposed at a second side of the base, wherein the second side is opposite to the first side. The storage device has a second electrical connector. The connecting member is connected to the storage device. The first fixing member is disposed on the connecting member. The second electrical connector is connected to the first electrical connector and the first fixing member is fixed to the first fixing portion, so as to fix the storage device on the base.

Abstract: A chip includes a substrate and a plurality of functional units on the substrate, in which each of the functional units has its own set of pads. The functional units are physically connected and there is no scribe line passes through the chip. A semiconductor structure having the chip is also disclosed.

Abstract: A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

Abstract: A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

Abstract: A 3D semiconductor device is provided, comprising plural memory layers vertically stacked on a substrate and parallel to each other; plural selection lines disposed on the memory layers and parallel to each other; plural bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; plural strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines.