Abstract: Disclosed is a histone acetyltransferase (HAT) inhibitor. Provided are a compound represented by the general formula I, a pharmaceutically acceptable salt, a stereoisomer, an enantiomer, a diastereoisomer, an atropisomer, a racemate, a polymorph, a solvate or an isotope-labeled compound (including deuterium substitution) thereof, a preparation method therefor, a pharmaceutical composition comprising same and use thereof in the treatment of various HAT-related diseases or conditions.

Abstract: A YTH N6-Methyladenosine RNA Binding Protein 1 (YTHDF1) attenuating agent, with a compound, and when bound to YTHDF1, the compound binds to amino acid residues 372-392, 479-494 and 526-535 of SEQ ID NO: 1. A modified antigen presenting cell (mAPC), with the mAPC being treated with a YTHDF1 attenuating agent. A composition, with a YTHDF1 attenuating agent, a mAPC treated with the YTHDF1 attenuating agent, and optionally a pharmaceutically acceptable carrier. A method for attenuating an activity of YTHDF1, by administering an effective amount of a YTHDF1 attenuating agent. A method for determining whether or not a candidate agent is a YTHDF1 attenuating agent, by contacting the candidate agent with a YTHDF1 mutant. A method for treating a disease, disorder or condition associated with an expression of an antigen in a subject in need thereof.

Abstract: A stacked packaging structure can include: a lead frame; a die located on a first surface of the lead frame; an electrical interconnection structure located above the die and configured to be electrically connected with corresponding electrodes of the die; a diode located on the electrical interconnection structure; and where a lower surface of the diode is electrically connected to the electrical interconnection structure, and the electrode on an upper surface of the diode is connected to the corresponding pins of the lead frame.

Abstract: A chip package assembly and a method for manufacturing the same are provided. A die is attached to one of pins located around a chip carrier, so that an electronic component such as a diode is packaged in the chip package assembly and is electrically connected in series with other dies inside the package, thereby improving the degree of integration of the chip package assembly, and reducing a volume of the external circuit.

Abstract: A method of forming a lead frame can include: providing a frame base; providing a substrate to support the frame base; and selectively etching the frame base to form first and second type pins. The first type pins are distributed in the central area of the lead frame, and the second type of the pins are distributed in the edge area of the lead frame. The first type pins are separated from the second type of the pins, and the first and second type pins are not connected by connecting bars. A pattern of a first surface of the first and second type pins is different from that of a second surface of the first and second type pins. The metal of the first surface is different from the metal of the second surface, and the second surface is opposite to the first surface.

Abstract: The present invention relates to a bromodomain inhibitor. Provided are a compound represented by general formula I or a pharmaceutically acceptable salt, enantiomer, diastereomer, atropisomer, racemate, polymorph, solvate, or isotopically labeled compound (including deuterium substitution) thereof, a preparation method of the same, a pharmaceutical composition comprising the same, and a pharmaceutical use thereof.

Abstract: A method of forming a lead frame can include: providing a frame base; providing a substrate to support the frame base; and selectively etching the frame base to form first and second type pins. The first type pins are distributed in the central area of the lead frame, and the second type of the pins are distributed in the edge area of the lead frame. The first type pins are separated from the second type of the pins, and the first and second type pins are not connected by connecting bars. A pattern of a first surface of the first and second type pins is different from that of a second surface of the first and second type pins. The metal of the first surface is different from the metal of the second surface, and the second surface is opposite to the first surface.

Abstract: Disclosed is a histone acetyltransferase (HAT) inhibitor. Provided are a compound represented by the general formula I, a pharmaceutically acceptable salt, a stereoisomer, an enantiomer, a diastereoisomer, an atropisomer, a racemate, a polymorph, a solvate or an isotope-labeled compound (including deuterium substitution) thereof, a preparation method therefor, a pharmaceutical composition comprising same and use thereof in the treatment of various HAT-related diseases or conditions.

Abstract: A chip package assembly and a method for manufacturing the same are provided. A die is attached to one of pins located around a chip carrier, so that an electronic component such as a diode is packaged in the chip package assembly and is electrically connected in series with other dies inside the package, thereby improving the degree of integration of the chip package assembly, and reducing a volume of the external circuit.

Abstract: Disclosed is a histone acetyltransferase (HAT) inhibitor. Provided are a compound represented by the general formula I, a pharmaceutically acceptable salt, a stereoisomer, an enantiomer, a diastereoisomer, an atropisomer, a racemate, a polymorph, a solvate or an isotope-labeled compound (including deuterium substitution) thereof, a preparation method therefor, a pharmaceutical composition comprising same and use thereof in the treatment of various HAT-related diseases or conditions.

Abstract: A chip package structure can include: a lead frame having a plurality of pins, a first die pad, and a second die pad; a first die and a second die, where a first surface of the first die is installed on the first die pad, and a first surface of the second die is installed on the second die pad; a plurality of pads installed on a second surface of the first die and a second surface of the second die; and bonding wires including a first set of bonding wires with each having one terminal connected to pads of the first die, and a second set of bonding wires with each having one terminal connected to pads of the second die for connectivity between the first die and the second die, and between the plurality of pins and the first die and the second die.

Abstract: A chip package assembly and a method for manufacturing the same are provided. A die is attached to one of pins located around a chip carrier, so that an electronic component such as a diode is packaged in the chip package assembly and is electrically connected in series with other dies inside the package, thereby improving the degree of integration of the chip package assembly, and reducing a volume of the external circuit.

Abstract: The present invention relates to a bromodomain inhibitor. Provided are a compound represented by general formula I or a pharmaceutically acceptable salt, enantiomer, diastereomer, atropisomer, racemate, polymorph, solvate, or isotopically labeled compound (including deuterium substitution) thereof, a preparation method of the same, a pharmaceutical composition comprising the same, and a pharmaceutical use thereof.

Abstract: A method of forming a lead frame can include: providing a frame base; providing a substrate to support the frame base; and selectively etching the frame base to form first and second type pins. The first type pins are distributed in the central area of the lead frame, and the second type of the pins are distributed in the edge area of the lead frame. The first type pins are separated from the second type of the pins, and the first and second type pins are not connected by connecting bars. A pattern of a first surface of the first and second type pins is different from that of a second surface of the first and second type pins. The metal of the first surface is different from the metal of the second surface, and the second surface is opposite to the first surface.

Abstract: A method of forming a chip package structure can include: forming a substrate; forming a first cavity in the substrate; and installing a first chip in the first cavity. The method can also include forming a second cavity in the substrate; and installing a second chip in the second cavity. The first cavity is located at a first side of the substrate, and the second cavity is located at a second side of the substrate, where the first side of the substrate is opposite to the second side of the substrate.

Abstract: A stacked semiconductor device including a first substrate, a first insulating layer located on the first substrate, a second insulating layer located on the first insulating layer, a second substrate located on the second insulating layer, an external connection via extending through the second substrate in a first direction perpendicular to an upper surface of the second substrate and exposing an external connection pad, the external connection pad being located in the first insulating layer or the second insulating layer, and a protective ring formed in the second insulating layer and arranged to at least partially surround a sidewall of the external connection via with the first direction as an axial direction, but not to be exposed from the sidewall of the external connection via.

Abstract: An image sensor comprises a pixel array, wherein at least one pixel cell in the pixel array comprises an imaging photosensitive element configured to convert a portion of incident light into charges for an image signal, and first and second phase detection photosensitive elements arranged side by side at one side of the imaging photosensitive element opposite to a light incident side and configured to convert light penetrating the imaging photosensitive element into charges for first and second phase detection signals respectively, wherein the first and second phase detection signals are used for focus detection.

Abstract: A method of manufacturing a semiconductor device comprises: providing a stacked structure comprising a first wafer that includes a first substrate, a first insulating layer and a first electrical connector and a second wafer that includes a second substrate, a second insulating layer and a second electrical connector; forming a first portion of a TSV which overlaps at least part of the first and second electrical connectors and exposes a part of a surface of the first insulating layer; forming an insulating film that at least covers side surfaces and a bottom surface of the first portion; forming a first conductive barrier film retained on the side surfaces of the first portion; forming a second portion of the TSV that exposes the first and second electrical connectors; forming a conductive plug in the first and second portions, to interconnect the first and second electrical connectors.

Abstract: A semiconductor device comprises an array of photosensitive elements and a grid. The grid is arranged on the array of photosensitive elements, defines an opening for receiving light respectively for each photosensitive element, and optically isolates each photosensitive element from its adjacent photosensitive elements. The grid may comprise an optical isolation portion and a dielectric portion above the optical isolation portion, wherein the dielectric portion defines a sidewall tilted at an angle toward an outer side of the opening. Methods of manufacturing semiconductor devices are also disclosed.

Abstract: A chip package assembly and a method for manufacturing the same are provided. A die is attached to one of pins located around a chip carrier, so that an electronic component such as a diode is packaged in the chip package assembly and is electrically connected in series with other dies inside the package, thereby improving the degree of integration of the chip package assembly, and reducing a volume of the external circuit.