Patents by Inventor Shijie Chen

Shijie Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120104506
    Abstract: There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO2, is interposed inside high-k gate dielectric layers of the CMOSFET device, and the threshold voltage is adjusted by means of the interface dipoles formed by the cap layer inside the high-k gate dielectric layers. According to the present invention, it is possible to effectively optimize the threshold voltage of the CMOSFET device without significantly increasing EOT thereof.
    Type: Application
    Filed: June 24, 2010
    Publication date: May 3, 2012
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Wenwu Wang, Huilong Zhu, Shijie Chen, Depeng Chen
  • Patent number: 8161775
    Abstract: In one aspect of the invention, an integrated hollow fabric structure includes a body having an axis and a thickness along a direction perpendicular to the axis, at least first and second groups of yarns, the yarns of each group space-regularly disposed in layers, where the yarn layers of the at least two groups of yarns are alternately stacked and interlocked together, and embedded in the body, and a third group of yarns through the thickness of the body to interlock the layers together, where the positions and the pattern of interlocking vary according to the need.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: April 24, 2012
    Assignees: Stoneferry Technology, LLC, Sinoma Science & Technology Ltd.
    Inventors: Zhong-Xing Mi, Qian Zhao, Youjiang Wang, Shijie Chen
  • Publication number: 20120076962
    Abstract: Integrated multiaxial articles have a prescribed integration pattern formed of winding yarns arranged in multiaxial direction at prescribed angles in a plurality of layers bound together by a set of through-the-layers binding yarns with yarns of non-crimp. Methods and apparatus of making same are presented. Hollow integrated multiaxial fabric and its variants are introduced.
    Type: Application
    Filed: December 6, 2011
    Publication date: March 29, 2012
    Applicants: SINOMA SCIENCE & TECHNOLOGY LTD., STONEFERRY TECHNOLOGY, LLC
    Inventors: Zhong-Xing Mi, Qian Zhao, Youjiang Wang, Shijie Chen
  • Publication number: 20120021596
    Abstract: The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.
    Type: Application
    Filed: September 28, 2010
    Publication date: January 26, 2012
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Kai Han, Wenwu Wang, Xiaolei Wang, Shijie Chen, Dapeng Chen
  • Publication number: 20120012939
    Abstract: The present invention provides a semiconductor device, comprising: a semiconductor substrate having a first region and a second region; a first gate structure belong to a PMOS device on the first region; a second gate structure belong to an nMOS device on the second region; a multiple-layer first sidewall spacer on sidewalls of the first gate structure, wherein a layer of the multiple-layer first sidewall spacer adjacent to the first gat structure is an oxide layer; a multiple-layer second sidewall spacer on sidewalls of the second gate structure, wherein a layer of the multiple layers of second sidewall spacer adjacent to the first gat structure is a nitride layer. Application of the present invention may alleviate the oxygen vacancy in a high-k gate dielectric in a pMOS device, and further avoid the problem of EOT growth of an nMOS device during the high-temperature thermal treatment process, and therefore effectively improve the overall performance of the high-k gate dielectric CMOS device.
    Type: Application
    Filed: June 23, 2010
    Publication date: January 19, 2012
    Applicant: INSTITUE OF MICROELELCTRONICS, CHINESE ACADEMY OF SCINECES
    Inventors: Wang Wenwu, Shijie Chen, Xiaolei Wang, Kai Han, Dapeng Chen
  • Publication number: 20110260255
    Abstract: The present invention relates to a method of manufacturing a semiconductor device. After depositing the metal gate electrode material, a layer of oxygen molecule catalyzing layer having a catalyzing function to the oxygen molecules is deposited, and afterwards, a low-temperature PMA annealing process is used to decompose the oxygen molecules in the annealing atmosphere into more active oxygen atoms. These oxygen atoms are diffused into the high-k gate dielectric film through the metal gate to supplement the oxygen vacancies in the high-k film, in order to alleviate oxygen vacancies in the high-k film and improve the quality of the high-k film. According to the present invention, the oxygen vacancies and defects of high-k gate dielectric film will be alleviated, and further, growth of SiOx interface layer having a low dielectric constant caused by the traditional PDA high temperature process may be prevented.
    Type: Application
    Filed: June 24, 2010
    Publication date: October 27, 2011
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Wenwu Wang, Shijie Chen, Xiaolei Wang, Kai Han, Dapeng Chen
  • Publication number: 20110254063
    Abstract: The present invention provides a MOS device, which comprises: a substrate; an interface layer thin film formed on the substrate; a high k gate dielectric layer formed on the interface layer thin film; and a metal gate formed on the high k gate dielectric layer. The metal gate comprises, upwardly in order, a metal gate work function layer, an oxygen absorption element barrier layer, a metal gate oxygen absorbing layer, a metal gate barrier layer and a polysilicon layer.
    Type: Application
    Filed: September 27, 2010
    Publication date: October 20, 2011
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Shijie Chen, Wenwu Wang, Xiaolei Wang, Kai Han
  • Publication number: 20110254093
    Abstract: A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility.
    Type: Application
    Filed: June 24, 2010
    Publication date: October 20, 2011
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Wenwu Wang, kai Han, Shijie Chen, Xiaolei Wang, Dapeng Chen
  • Publication number: 20110227163
    Abstract: The present invention relates to a semiconductor device. Interface layers of different thickness or different materials are used in the NMOS region and the PMOS region of the semiconductor substrate, which not only effectively reduce EOT of the device, especially EOT of the PMOS device, but also increase the electron mobility of the device, especially the electron mobility of the NMOS device, thereby effectively improving the overall performance of the device.
    Type: Application
    Filed: June 23, 2010
    Publication date: September 22, 2011
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Wengwu Wang, Shijie Chen, Kai Han, Xiaolei Wang, Dapeng Chen
  • Publication number: 20110169097
    Abstract: There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; an interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer. According to to the present invention, the very thin metal layers are deposited between the high-k gate dielectric layers for NMOS and PMOS devices respectively, such that a flat band voltage of the device is adjusted by means of positive or negative charges generated by the metal layers inside the high-k gate dielectric layers, and thus the threshold voltage of the device is controlled.
    Type: Application
    Filed: June 24, 2010
    Publication date: July 14, 2011
    Inventors: Wenwu Wang, Huilong Zhu, Shijie Chen, Dapeng Chen
  • Publication number: 20110165350
    Abstract: In one aspect of the invention, an integrated hollow fabric structure includes a body having an axis and a thickness along a direction perpendicular to the axis, at least first and second groups of yarns, the yarns of each group space-regularly disposed in layers, where the yarn layers of the at least two groups of yarns are alternately stacked and interlocked together, and embedded in the body, and a third group of yarns through the thickness of the body to interlock the layers together, where the positions and the pattern of interlocking vary according to the need.
    Type: Application
    Filed: March 16, 2011
    Publication date: July 7, 2011
    Applicants: STONEFERRY TECHNOLOGY, LLC, SINOMA SCIENCE & TECHNOLOGY LTD.
    Inventors: Zhong-Xing Mi, Qian Zhao, Youjiang Wang, Shijie Chen
  • Patent number: 5253607
    Abstract: This invention relates to a one-step formed all-plastic boat, the entire hull of which is comprised of plastic material that contains in addition small amounts of an additive and a filler. The hull has a cavity, divisional cavities, open and closed compartments, but no welded parts. The process of manufacturing the all-plastic boat comprises feeding physically modified resinous material into a closed container type boat mold, subjecting the mold to a complex motion of circular and semicircular rotations of 360.degree.-180.degree. and rockings of selected positional angles; applying an operational heat treatment at 200.degree.-450.degree. C. to the mold while the mold undergoes the complex movements; and after heat treatment, cooling the mold and then releasing the entire all-plastic boat.
    Type: Grant
    Filed: May 14, 1991
    Date of Patent: October 19, 1993
    Inventor: Shijie Chen