Abstract: An image sensor and a forming method thereof are disclosed. The image sensor includes: a semiconductor substrate, the semiconductor substrate has photodiodes therein; and a dielectric layer, the dielectric layer is located on a surface of the semiconductor substrate; and photoelectric conversion films formed in the dielectric layer, wherein the photoelectric conversion films are in one-to-one correspondence aligned with the photodiodes, so that light passing through the photodiodes is transmitted to the corresponding photoelectric conversion films. The solution provided in the present disclosure can effectively improve the quantum efficiency of the image sensor. The photoelectric conversion films are made of organic photoelectric materials. The photoelectric conversion films have photosensitive area, which is equal or larger than the photosensitive area of the corresponding photodiode.

Abstract: The application disclosed a semiconductor image sensor and a preparation method thereof. The semiconductor image sensor includes: a semiconductor substrate, a buffer layer formed on the semiconductor substrate; and a potential regulation laminated structure, formed on the buffer layer, and configured to regulate a surface potential of the semiconductor substrate. The potential regulation laminated structure includes a first potential regulation layer formed on the buffer layer, a second potential regulation layer formed on the first potential regulation layer and a third potential regulation layer formed on the second potential regulation layer, wherein the first potential regulation layer includes a high-k dielectric constant material layer, and the second and third potential regulation layers each include either a conductive material layer or a high-k dielectric constant material layer.

Abstract: A chip package structure can include: a lead frame having a plurality of pins, a first die pad, and a second die pad; a first die and a second die, where a first surface of the first die is installed on the first die pad, and a first surface of the second die is installed on the second die pad; a plurality of pads installed on a second surface of the first die and a second surface of the second die; and bonding wires including a first set of bonding wires with each having one terminal connected to pads of the first die, and a second set of bonding wires with each having one terminal connected to pads of the second die for connectivity between the first die and the second die, and between the plurality of pins and the first die and the second die.

Abstract: A method of forming a chip package structure can include: forming a substrate; forming a first cavity in the substrate; and installing a first chip in the first cavity. The method can also include forming a second cavity in the substrate; and installing a second chip in the second cavity. The first cavity is located at a first side of the substrate, and the second cavity is located at a second side of the substrate, where the first side of the substrate is opposite to the second side of the substrate.

Abstract: The present disclosure provides a heat spreader and a power module. The heat spreader comprises: a base plate comprising a first surface and a second surface opposite to the first surface; an insulating frame fixedly connected to the first surface of the base plate; and an insulating material attached to at least a part of a surface of the insulating frame. The present disclosure can effectively satisfy design requirements for both heat dissipation and insulation, and significantly increase a layout space for a printed circuit board.

Abstract: A modular power supply and a method for manufacturing the same are disclosed. The modular power supply comprises a printed circuit board, power components, and a heat sink. The power components are mounted on the printed circuit board and disposed at a side opposite to the heat sink, a lower surface of the printed circuit board is engaged with an upper surface of the heat sink which is planar, and an insulating layer is disposed between the upper surface of the heat sink and the lower surface of the printed circuit board. A method for manufacturing the modular power supply is also disclosed. The modular power supply has excellent heat dissipation effect, and the production and assembly process thereof is simplified, so that the production efficiency is improved and the quality is guaranteed.

Abstract: The present disclosure provides a heat spreader and a power module. The heat spreader comprises: a base plate comprising a first surface and a second surface opposite to the first surface; an insulating frame fixedly connected to the first surface of the base plate; and an insulating material attached to at least a part of a surface of the insulating frame. The present disclosure can effectively satisfy design requirements for both heat dissipation and insulation, and significantly increase a layout space for a printed circuit board.

Abstract: A modular power supply and a method for manufacturing the same are disclosed. The modular power supply comprises a printed circuit board, power components, and a heat sink. The power components are mounted on the printed circuit board and disposed at a side opposite to the heat sink, a lower surface of the printed circuit board is engaged with an upper surface of the heat sink which is planar, and an insulating layer is disposed between the upper surface of the heat sink and the lower surface of the printed circuit board. A method for manufacturing the modular power supply is also disclosed. The modular power supply has excellent heat dissipation effect, and the production and assembly process thereof is simplified, so that the production efficiency is improved and the quality is guaranteed.

Abstract: The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.

Abstract: The present invention provides a semiconductor device, comprising: a semiconductor substrate having a first region and a second region; a first gate structure belong to a PMOS device on the first region; a second gate structure belong to an nMOS device on the second region; a multiple-layer first sidewall spacer on sidewalls of the first gate structure, wherein a layer of the multiple-layer first sidewall spacer adjacent to the first gat structure is an oxide layer; a multiple-layer second sidewall spacer on sidewalls of the second gate structure, wherein a layer of the multiple layers of second sidewall spacer adjacent to the first gat structure is a nitride layer. Application of the present invention may alleviate the oxygen vacancy in a high-k gate dielectric in a pMOS device, and further avoid the problem of EOT growth of an nMOS device during the high-temperature thermal treatment process, and therefore effectively improve the overall performance of the high-k gate dielectric CMOS device.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. After depositing the metal gate electrode material, a layer of oxygen molecule catalyzing layer having a catalyzing function to the oxygen molecules is deposited, and afterwards, a low-temperature PMA annealing process is used to decompose the oxygen molecules in the annealing atmosphere into more active oxygen atoms. These oxygen atoms are diffused into the high-k gate dielectric film through the metal gate to supplement the oxygen vacancies in the high-k film, in order to alleviate oxygen vacancies in the high-k film and improve the quality of the high-k film. According to the present invention, the oxygen vacancies and defects of high-k gate dielectric film will be alleviated, and further, growth of SiOx interface layer having a low dielectric constant caused by the traditional PDA high temperature process may be prevented.

Abstract: A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment.

Abstract: There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO2, is interposed inside high-k gate dielectric layers of the CMOSFET device, and the threshold voltage is adjusted by means of the interface dipoles formed by the cap layer inside the high-k gate dielectric layers. According to the present invention, it is possible to effectively optimize the threshold voltage of the CMOSFET device without significantly increasing EOT thereof.

Abstract: There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; am interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the very thin metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer.

Abstract: Integrated multiaxial articles are formed of yarns arranged in multiaxial direction in a plurality of layers bound together by a set of through-the-layers yarns. Methods and apparatus of making same are presented. Hollow integrated multiaxial fabric and its variants are introduced.

Abstract: A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment.

Abstract: A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility.

Abstract: There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO2, is interposed inside high-k gate dielectric layers of the CMOSFET device, and the threshold voltage is adjusted by means of the interface dipoles formed by the cap layer inside the high-k gate dielectric layers. According to the present invention, it is possible to effectively optimize the threshold voltage of the CMOSFET device without significantly increasing EOT thereof.

Abstract: In one aspect of the invention, an integrated hollow fabric structure includes a body having an axis and a thickness along a direction perpendicular to the axis, at least first and second groups of yarns, the yarns of each group space-regularly disposed in layers, where the yarn layers of the at least two groups of yarns are alternately stacked and interlocked together, and embedded in the body, and a third group of yarns through the thickness of the body to interlock the layers together, where the positions and the pattern of interlocking vary according to the need.

Abstract: Integrated multiaxial articles have a prescribed integration pattern formed of winding yarns arranged in multiaxial direction at prescribed angles in a plurality of layers bound together by a set of through-the-layers binding yarns with yarns of non-crimp. Methods and apparatus of making same are presented. Hollow integrated multiaxial fabric and its variants are introduced.