Abstract: Memories are provided. A memory includes a first memory array, a second memory array and a read circuit. The first memory array is configured to store first data. The second memory array is configured to store second data that is complementary to the first data. The read circuit includes a decoding circuit, a sensing circuit and an output buffer. The decoding circuit is configured to provide a first signal according to the first data and a second signal according to the second data in response to an address signal. The sensing circuit is configured to provide a first sensing signal according to a reference signal and the first signal, and a second sensing signal according to the reference signal and the second signal. The output buffer is configured to provide the first sensing signal or the second sensing signal as an output according to a control signal.

Abstract: A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.

Abstract: A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a word line program signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a word line read signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the word line program signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the word line read signal; a first word line to selectively provide the word line program signal; a second word line to selectively provide the word line read signal; and a bit line.

Abstract: Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.

Abstract: An IC device includes an anti-fuse device including a dielectric layer between a first gate structure and an active area, a first transistor including a second gate structure overlying the active area, and a second transistor including a third gate structure overlying the active area. The first gate structure is between the second gate structure and the third gate structure.

Abstract: A memory bit cell includes a first memory cell including a first antifuse transistor and a first selection transistor, the first antifuse transistor being selectable between a first state or a second state in response to a first signal, the first selection transistor being configured to provide access to the first antifuse transistor in response to a second signal; a second memory cell including a second antifuse transistor and a second selection transistor, the second antifuse transistor being selectable between the first state or the second state in response to the first signal, the second selection transistor being configured to provide access to the second antifuse transistor in response to the second signal; a first word line to selectively provide the first signal; a second word line to selectively provide the second signal; and a bit line for sensing the first state or the second state.

Abstract: Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.

Abstract: An IC device includes an anti-fuse device including a dielectric layer between a first gate structure and an active area, a first transistor including a second gate structure overlying the active area, and a second transistor including a third gate structure overlying the active area. The first gate structure is between the second gate structure and the third gate structure.

Abstract: A memory circuit array includes a first read device and a first program device. The first read device is coupled to a first bit line. The first read device includes a first transistor coupled to a first word line, and a second transistor coupled to the first word line. The first program device is coupled to the first read device. The first program device includes a third transistor coupled to a second word line, and a fourth transistor coupled to the second word line.

Abstract: A structure for integrating a field-effect transistor (FET) and a heterojunction bipolar transistor (HBT) is provided. The structure includes: a substrate; a first epitaxial structure located on the substrate, having a part of the HBT; and a second epitaxial structure located on the first epitaxial structure, having a part of the FET.

Abstract: In one embodiment, a method comprises receiving from an initiating user a request for information of a target user, accessing information associated with the initiating user comprising one or more attributes, determining whether the initiating user is permitted to access information related to the target user based on privacy settings of the target user, wherein the privacy settings require the initiating user attributes to satisfy one or more social, spatiotemporal, geographic, or temporal conditions, and blocking the initiating user from accessing information of the target user in response to determining that the initiating user does not fulfill the requirements of the privacy settings of the target user.

Abstract: In one embodiment, a social networking system provides people look up service and establish anonymous communication session between users; creates contact association for future communication between users; and configures one or more privacy settings for users. The method may comprise receiving from an initiating user a request for information of a target user, determining location information associated with the initiating user, accessing one or more privacy settings of the target user to determine if the initiating user fulfills a requirement based on one or more social, spatiotemporal, geographic or temporal conditions associated with the target user and the location information associated with the initiating user, and in response to determining that the initiating user fulfills the requirement, providing the requested information of the target user to the initiating user.

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.

Abstract: An electrical contact limiter structure of wire connection terminal has a simplified structure and is easy to operate to enhance the stability of the operation and motion of a metal leaf spring. The wire connection terminal includes conductive components mounted in the insulation case and electrical contact assembled with the conductive components. The electrical contact has a limiter for receiving the metal leaf spring and restricting moving path thereof. The limiter is partitioned into at least one space. A limitation mechanism is assembled with the limiter. The metal leaf spring is mounted in the space. The wiring circuits or conductive wires coming from an apparatus can be easily directly plugged into the space of the limiter to insert with the metal leaf spring. The limiter and the limitation mechanism cooperatively prevent the metal leaf spring from being deflected and over-bent and damaged in operation.

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes a first decoder coupled to the first memory array, a second decoder coupled to the second memory array, and an output buffer. The first decoder obtains first data from the first memory array according a first address signal. The second decoder obtains second data from the second memory array according the first address signal. The output buffer selectively provides the first data or the second data as an output according to a control signal. The first data is complementary to the second data.

Abstract: An electrical contact limiter structure of wire connection terminal has a simplified structure and is easy to operate to enhance the stability of the operation and motion of a metal leaf spring. The wire connection terminal includes conductive components mounted in the insulation case and electrical contact assembled with the conductive components. The electrical contact has a limiter for receiving the metal leaf spring and restricting moving path thereof. The limiter is partitioned into at least one space. A limitation mechanism is assembled with the limiter. The metal leaf spring is mounted in the space. The wiring circuits or conductive wires coming from an apparatus can be easily directly plugged into the space of the limiter to insert with the metal leaf spring. The limiter and the limitation mechanism cooperatively prevent the metal leaf spring from being deflected and over-bent and damaged in operation.

Abstract: An unmanned aerial vehicle including a feeling-effect showing device is provided. The feeling-effect showing device is adapted for showing a feeling effect such as a visual effect and/or an audio effect. In addition, a method of using a plurality of unmanned aerial vehicles to show a feeling effect is also provided.

Abstract: A switch wire connection device has a simplified structure and is easy to operate with enhanced stability of operation. The switch wire connection device includes a conductive component mounted in an insulation case, a switch pushbutton assembled with the conductive component and an electrical contact. The electrical contact has a restriction unit and a contact plate connected with the restriction unit. By means of operating the pushbutton, the conductive component is driven to selectively electrically contact or separate from the contact plate. The restriction unit defines a space, in which a metal leaf spring is assembled. The wiring circuit or conductive wire of a machine or equipment can be easily directly plugged into the space of the restriction unit and held by the metal leaf spring. The metal leaf spring is prevented from deflecting in the operation process.

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes a first decoder coupled to the first memory array, a second decoder coupled to the second memory array, and an output buffer. The first decoder obtains first data from the first memory array according a first address signal. The second decoder obtains second data from the second memory array according the first address signal. The output buffer selectively provides the first data or the second data as an output according to a control signal. The first data is complementary to the second data.