Abstract: A reactive pre-clean chamber that contains a wafer heating apparatus, such as a high-temperature electrostatic chuck (HTESC), for directly heating a wafer supported on the apparatus during a pre-cleaning process. The wafer heating apparatus is capable of heating the wafer to the optimum temperatures required for a hydrogen plasma reactive pre-clean (RPC) process. Furthermore, degassing and pre-cleaning can be carried out in the same pre-clean chamber. The invention further includes a method of pre-cleaning a wafer using a pre-clean chamber that contains a wafer heating apparatus.

Abstract: Within a microelectronic fabrication and a method for fabricating the microelectronic fabrication a barrier layer is formed over a substrate. Within the method and the microelectronic fabrication the barrier layer is formed of a refractory metal nitride barrier material having within its thickness a gradient in nitrogen concentration. The barrier layer has low resistivity and improved electromigration performance.

Abstract: A loadlock. The loadlock for wafers includes a chamber, a pedestal, a retractable shaft, and a bellows. The chamber has a plurality of walls and a bottom surface. The pedestal supports a cassette and is disposed in the chamber. The retractable shaft has a top end and a bottom end. The top end is connected to the pedestal and the bottom end is connected to the bottom surface as a reference for positioning the pedestal. The bellows has a first end and a second end. The first end is disposed on the pedestal and the second end is sealed at the bottom end of the retractable shaft. Preferably, the retractable shaft is fully enclosed by the bellows.

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.

Abstract: A method for preventing carbon and nitrogen penetration from a deposited overlayer into a dielectric insulating layer to improve a subsequent photolithographic patterning and anisotropic etching process including providing a semiconductor wafer having a process surface including an exposed dielectric insulating layer; and, subjecting the dielectric insulating layer to a hydrogen containing plasma treatment to form a penetration resistance to one of nitrogen containing and carbon containing species.

Abstract: Within a microelectronic fabrication and a method for fabricating the microelectronic fabrication a barrier layer is formed over a substrate. Within the method and the microelectronic fabrication the barrier layer is formed of a refractory metal nitride barrier material having within its thickness a gradient in nitrogen concentration. The barrier layer has low resistivity and improved electromigration performance.

Abstract: A method for preventing carbon and nitrogen penetration from a deposited overlayer into a dielectric insulating layer to improve a subsequent photolithographic patterning and anisotropic etching process including providing a semiconductor wafer having a process surface including an exposed dielectric insulating layer; and, subjecting the dielectric insulating layer to a hydrogen containing plasma treatment to form a penetration resistance to one of nitrogen containing and carbon containing species.

Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.

Abstract: A method for avoiding plasma arcing during a reactive ion etching (RIE) process including providing a semiconductor wafer having a process surface for depositing a dielectric insulating layer; depositing at least a portion of a dielectric insulating layer to form a deposition layer according to plasma assisted chemical vapor deposition (CVD) process; treating the deposition layer portion with a hydrogen plasma treatment to reduce an electrical charge nonuniformity of the deposition layer including applying a biasing power to the semiconductor wafer; and, carrying out a subsequent reactive ion etching process.

Abstract: A method for fabricating a microelectronic fabrication provides for forming a patterned conductor layer into a via defined by a pair of dielectric layers. Within the method, the via is plasma treated prior to forming therein the patterned conductor layer with at least one of: (1) an argon containing plasma with each of a radio frequency source power density and a radio frequency bias power density of less than about 300 watts; and (2) a hydrogen containing plasma with a radio frequency source power of greater than about 400 watts and a radio frequency bias power density of greater than about 100 watts.

Abstract: Low-strength plasma treatment for interconnects is disclosed. A low k dielectric-metal interconnect is formed that has a top surface, via a damascene process, such as a single- or a dual-damascene process. The top surface of the low k dielectric-metal interconnect is low-power plasma treated to substantially cure any damage to the top surface resulting from the damascene process. Such damage may include the entrapment of metal ions, such as copper ions where the metal of the interconnect is copper, and chemical-mechanical planarization (CMP) materials resulting from the CMP employed during the damascene process, within the top surface of the low k dielectric-metal interconnect. The low-power plasma used may be helium plasma.