Patents by Inventor Shing-Chyang Pan
Shing-Chyang Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7805258Abstract: A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer.Type: GrantFiled: February 16, 2007Date of Patent: September 28, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Hung Fu, Chih-Wei Chang, Shih-Chang Chen, Chin-Piao Chang, Shing-Chyang Pan, Wei-Jung Lin, Tsung-Hsun Huang
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Patent number: 7704886Abstract: A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.Type: GrantFiled: February 14, 2008Date of Patent: April 27, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Lin Su, Shing-Chyang Pan, Cheng-Lin Huang, Ching-Hua Hsieh
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Publication number: 20090209106Abstract: A method of forming a seed layer of an interconnect structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form the seed layer; and in-situ performing a first etch step to remove a portion of the seed layer. The method may further includes additional deposition and etch steps for forming the seed layer.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Inventors: Li-Lin Su, Cheng-Lin Huang, Shing-Chyang Pan, Ching-Hua Hsieh
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Publication number: 20090209098Abstract: A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Inventors: Li-Lin Su, Shing-Chyang Pan, Cheng-Lin Huang, Ching-Hua Hsieh
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Publication number: 20090047780Abstract: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.Type: ApplicationFiled: October 10, 2008Publication date: February 19, 2009Inventors: Cheng-Lin Huang, Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Chao-Hsien Peng, Li-Lin Su, Jing-Cheng Lin, Shao-Lin Shue, Mong-Song Liang
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Patent number: 7453149Abstract: A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.Type: GrantFiled: December 28, 2004Date of Patent: November 18, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Lin Huang, Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Chao-Hsien Peng, Li-Lin Su, Jing-Cheng Lin, Shao-Lin Shue, Mong-Song Liang
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Publication number: 20080199978Abstract: A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Inventors: Hsueh-Hung Fu, Chih-Wei Chang, Shih-Chang Chen, Chin-Piao Chang, Shing-Chyang Pan, Wei-Jung Lin, Tsung-Hsun Huang
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Publication number: 20070181434Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle ? less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.Type: ApplicationFiled: April 6, 2007Publication date: August 9, 2007Inventors: Hsien-Ming Lee, Jing-Cheng Lin, Shing-Chyang Pan, Ming-Hsing Tsai, Hung-Wen Su, Shih-Wei Chou, Shau-Lin Shue, Kuo-Wei Cheng, Ting-Chu Ko
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Patent number: 7253501Abstract: A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.Type: GrantFiled: August 3, 2004Date of Patent: August 7, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Ming Lee, Jing-Cheng Lin, Shing-Chyang Pan, Ching-Hua Hsieh, Chao-Hsien Peng, Cheng-Lin Huang, Li-Lin Su, Shau-Lin Shue
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Patent number: 7247252Abstract: A method for avoiding plasma arcing during a reactive ion etching (RIE) process including providing a semiconductor wafer having a process surface for depositing a dielectric insulating layer; depositing at least a portion of a dielectric insulating layer to form a deposition layer according to plasma assisted chemical vapor deposition (CVD) process; treating the deposition layer portion with a hydrogen plasma treatment to reduce an electrical charge nonuniformity of the deposition layer including applying a biasing power to the semiconductor wafer; and, carrying out a subsequent reactive ion etching process.Type: GrantFiled: June 20, 2002Date of Patent: July 24, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shing-Chyang Pan, Yu-Chun Huang, Shwangming Jing
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Patent number: 7226860Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle ? less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.Type: GrantFiled: April 28, 2004Date of Patent: June 5, 2007Assignee: Taiwan Semiconductor Manfacturing Co. Ltd.Inventors: Hsien-Ming Lee, Jing-Cheng Lin, Shing-Chyang Pan, Ming-Hsing Tsai, Hung-Wen Su, Shih-Wei Chou, Shau-Lin Shue, Kuo-Wei Cheng, Ting-Chu Ko
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Patent number: 7193327Abstract: An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.Type: GrantFiled: January 25, 2005Date of Patent: March 20, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Shing-Chyang Pan, Shau-Lin Shue, Ching-Hua Hsieh, Cheng-Lin Huang, Hsien-Ming Lee, Jing-Cheng Lin
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Publication number: 20060244151Abstract: Semiconductor devices having an oblique metal recess for receiving metal during metallization processes are described. In one example, a semiconductor device includes a dielectric layer formed over a conductive pad disposed in a substrate. The conductive pad is etched to include an oblique recess, which interfaces with a metal deposited during a metallization process. Related methods for forming such metal contacts and interconnections for the semiconductor device are also described.Type: ApplicationFiled: May 2, 2005Publication date: November 2, 2006Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: CHEN-HUA YU, CHENG-LIN HUANG, SHAU-LIN SHUE, CHING-HUA HSIEH, SHING-CHYANG PAN, HSIEN-MING LEE LEE, HSUEH-HUNG FU
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Publication number: 20060163746Abstract: An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the trench is greater than about 0.55. In another embodiment, the ratio of the thickness of the barrier layers along a sidewall approximately midway between the bottom of the trench and the top of the dielectric layer to the thickness of the barrier layers along the bottom of the via is greater than about 1.0. An underlying conductive layer may be recessed.Type: ApplicationFiled: January 25, 2005Publication date: July 27, 2006Inventors: Chen-Hua Yu, Shing-Chyang Pan, Shau-Lin Shue, Ching-Hua Hsieh, Cheng-Lin Huang, Hsien-Ming Lee, Jing-Cheng Lin
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Patent number: 7030023Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.Type: GrantFiled: September 4, 2003Date of Patent: April 18, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shing-Chyang Pan, Ching-Hua Hsieh, Jing-Cheng Lin, Hsien-Ming Lee, Cheng-Lin Huang, Shau-Lin Shue
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Publication number: 20060027925Abstract: A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.Type: ApplicationFiled: December 28, 2004Publication date: February 9, 2006Inventors: Cheng-Lin Huang, Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Chao-Hsien Peng, Li-Lin Su, Jing-Cheng Lin, Shao-Lin Shue, Mong-Song Liang
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Publication number: 20060027922Abstract: A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the conductive lines. An interface region may be formed over the top surface of the conductive lines, the interface region including the metal element of the cap layer. The cap layer prevents the conductive material in the conductive lines from migrating or diffusing into adjacent subsequently formed insulating material layers. The cap layer may also function as an etch stop layer.Type: ApplicationFiled: August 3, 2004Publication date: February 9, 2006Inventors: Hsien-Ming Lee, Jing-Cheng Lin, Shing-Chyang Pan, Ching-Hua Hsieh, Chao-Hsien Peng, Cheng-Lin Huang, Li-Lin Su, Shau-Lin Shue
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Publication number: 20050263891Abstract: A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying conductive layer such that the trenches have varying widths. The vias are lined with a first barrier layer. The first barrier layers along the bottom of vias are removed such that a recess formed in the underlying conductive layer. The recesses formed along the bottom of vias are such that the recess below narrower trenches is greater than the recess formed below wider trenches. In another embodiment, a second barrier layer may then be formed over the first barrier layer. In this embodiment, a portion of the conductive layer may be interposed between the first barrier layer and the second barrier layer.Type: ApplicationFiled: April 7, 2005Publication date: December 1, 2005Inventors: Bih-Huey Lee, Hong-Yuan Chu, Ping-Kun Wu, Ching-Wen Lu, Jing-Cheng Lin, Shau-Lin Shue, Shing-Chyang Pan
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Publication number: 20050245072Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle ? less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Inventors: Hsien-Ming Lee, Jing-Cheng Lin, Shing-Chyang Pan, Ming-Hsing Tsai, Hung-Wen Su, Shih-Wei Chou, Shau-Lin Shue, Kuo-Wei Cheng, Ting-Chu Ko
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Patent number: RE41935Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.Type: GrantFiled: January 19, 2007Date of Patent: November 16, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shing-Chyang Pan, Keng-Chu Lin, Wen-Chih Chiou, Shwang-Ming Jeng