Patents by Inventor Shing Wong

Shing Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150141664
    Abstract: The invention relates to solution-processable, p-type, low-optical gap oligothiophene compounds for use in solar cell application, comprising at least one thiophene-containing group, at least one electron-withdrawing dicyanovinyl or tricyanovinyl group, and at least one electron-donating diphenylaminofluorenyl or N-alkylcarbazole group.
    Type: Application
    Filed: January 29, 2015
    Publication date: May 21, 2015
    Inventors: Ricky Man-Shing Wong, Weifeng Zhang, Lei Guo
  • Patent number: 9006066
    Abstract: A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Min-Hwa Chi, Hoong Shing Wong
  • Publication number: 20150099336
    Abstract: Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. A method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, epitaxially growing a silicon material on the fin structures, wherein a merged source/drain region is formed on the fin structures, and anisotropically etching at least one of the merged source drain regions to form an un-merged source/drain region.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Inventors: Hoong Shing Wong, Min-hwa Chi
  • Patent number: 8997301
    Abstract: An oral care implement that emits a scent. In one aspect, the invention is directed to a toothbrush comprising: a base component having a gripping region and an oral engaging region, wherein said base component comprises a first scenting agent; and a second component covering at least a portion of said base component in said gripping region, to control a rate of release of said first scenting agent from said base component in said gripping region.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 7, 2015
    Assignee: Colgate-Palmolive Company
    Inventors: Chi Shing Wong, Douglas J. Hohlbein, Kenneth Waguespack, Al Sprosta, Wen Jin Xi, Xiangji Ding
  • Patent number: 8975419
    Abstract: The invention relates to solution-processable, p-type, low-optical gap oligothiophene compounds for use in solar cell application, comprising at least one thiophene-containing group, at least one electron-withdrawing dicyanovinyl or tricyanovinyl group, and at least one electron-donating diphenylaminofluorenyl or N-alkylcarbazole group.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 10, 2015
    Assignee: Nano and Advanced Materials Institute Limited
    Inventors: Ricky Man-Shing Wong, Weifeng Zhang, Lei Guo
  • Patent number: 8967161
    Abstract: Described herein are dental floss compositions comprising an elastomeric matrix containing one or more particles, and methods of making and using the same.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: March 3, 2015
    Assignee: Colgate-Palmolive Company
    Inventors: Chi Shing Wong, Jose Eder Fontana, Paulo Focassio
  • Patent number: 8946029
    Abstract: Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. For example, a method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, forming disposable spacers on vertical sidewalls of the fin structures, and depositing a silicon oxide material over the fins and over the disposable spacers. The method further includes anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material, and etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched. Still further, the method includes epitaxially growing a silicon material in the void and on the un-etched fin structure.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Hoong Shing Wong, Min-hwa Chi
  • Patent number: 8940650
    Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Huy Cao, Huang Liu, Hoong Shing Wong, Songkram Srivathanakul, Sandeep Gaan
  • Publication number: 20150021694
    Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a chamfered surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Kristina Trevino, Yuan-Hung Lin, Gabriel Padron Wells, Chang Ho Maeng, Taejoon Han, Hoong Shing Wong
  • Patent number: 8906768
    Abstract: For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin from a bulk silicon substrate at one or more of the source and drain, and further performing SEG on one or more of the source and drain to form a wrap around epitaxial growth stressor that stresses a channel connecting the source and drain. The formed stressor can be formed so that the epitaxial growth material defining a wrap around configuration connects to the bulk substrate. The formed stressor can increase mobility in a channel connecting the defined source and drain.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Hoong Shing Wong, Min-hwa Chi
  • Publication number: 20140319615
    Abstract: A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 30, 2014
    Applicant: GLOBAL FOUNDRIES, Inc.
    Inventors: Min-Hwa CHI, Hoong Shing WONG
  • Publication number: 20140264489
    Abstract: For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin from a bulk silicon substrate at one or more of the source and drain, and further performing SEG on one or more of the source and drain to form a wrap around epitaxial growth stressor that stresses a channel connecting the source and drain. The formed stressor can be formed so that the epitaxial growth material defining a wrap around configuration connects to the bulk substrate. The formed stressor can increase mobility in a channel connecting the defined source and drain.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hoong Shing WONG, Min-hwa CHI
  • Publication number: 20140256141
    Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 11, 2014
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Huy Cao, Huang Liu, Hoong Shing Wong, Songkram Srivathanakul, Sandeep Gaan
  • Patent number: 8803682
    Abstract: In a system for protecting a user from injury sustained during sleep, a sensing device is operated to automatically monitor orientation or posture of a user during sleep of the user. A signal is transmitted from the sensing device to a control unit, which is operated to activate an appliance so that the appliance generates an alert signal upon detection by the sensing device and control unit of an undesirable orientation or posture of the user.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 12, 2014
    Assignee: J.T. Labs Limited
    Inventors: Tit-Shing Wong, Sui-kay Wong, Lewie Wai-choi Leung
  • Publication number: 20140212046
    Abstract: Two different approaches for reducing the bit depth of the image data so as to reduce the computation and hardware requirement of image patch matching, with minimal loss of matching accuracy are described. Patch matching is able to be implemented in many different ways, but generally involves matching one area of an image with another area of the same image or another area of a different image (e.g. another video frame) through the use of a matching cost function. Transforming the image data to lower bit depth, image processing techniques are able to be implemented to minimize the needed memory and other resources for patch-matching. The complexity/performance trade-off of the approaches are also adjustable so that they are able to be applied for applications with different quality requirements and hardware constraints.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: SONY CORPORATION
    Inventors: Tak Shing Wong, Alexander Berestov, Xiaogang Dong
  • Publication number: 20140205448
    Abstract: An exhaust diffuser and method for manufacturing an exhaust diffuser is provided. An exhaust diffuser for a torque-generating turbine, in particular a torque-generating gas turbine is provided herein. The exhaust diffuser having an inner member, the inner member having an outer surface and an outer member having an inner surface, the inner member and the outer member forming an annular channel, at least a first supporting strut connecting the inner member and the outer member, the first supporting strut extending essentially radially from the inner surface to the outer surface, the first supporting strut having a middle section having a first airfoil and an outer section having a second airfoil, and the second airfoil differing from the first airfoil in shape to be able to handle a higher range of angle of attack. Furthermore, it is described a method for manufacturing an exhaust diffuser.
    Type: Application
    Filed: August 1, 2012
    Publication date: July 24, 2014
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Li Shing Wong
  • Publication number: 20140174052
    Abstract: An exhaust diffuser and method for manufacturing an exhaust diffuser is provided. An exhaust diffuser for a torque-generating turbine, in particular a torque-generating gas turbine is provided, the exhaust diffuser having an inner member, and the inner member having an outer surface. The outer member having an inner surface, and the inner member and the outer member forming an annular channel at least a first supporting strut connecting the inner member and the outer member, the supporting strut extending essentially radially from the inner surface to the outer surface, the supporting strut having a middle section, the middle section having a first airfoil and an outer section having a second airfoil, and the second airfoil having a higher angle of incidence than the first airfoil. Furthermore, it is described a method for manufacturing an exhaust diffuser.
    Type: Application
    Filed: August 1, 2012
    Publication date: June 26, 2014
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Li Shing Wong
  • Patent number: 8745805
    Abstract: Toothbrushes comprising components with light transmitting and structural characteristics provide enhanced visual and other sensory effects. The components in combination are generally chemically compatible and function to provide areas of varying visibility of features. At least one of the components may include a scenting agent.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: June 10, 2014
    Assignee: Colgate-Palmolive Company
    Inventors: Chi Shing Wong, Douglas J. Hohlbein, Kenneth Waguespack, Al Sprosta, Wen Jin Xi, Xiangji Ding
  • Publication number: 20140134814
    Abstract: Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. For example, a method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, forming disposable spacers on vertical sidewalls of the fin structures, and depositing a silicon oxide material over the fins and over the disposable spacers. The method further includes anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material, and etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched. Still further, the method includes epitaxially growing a silicon material in the void and on the un-etched fin structure.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 15, 2014
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Hoong Shing Wong, Min-hwa Chi
  • Publication number: 20140131777
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a fin over a semiconductor substrate. The method further includes selectively epitaxially growing a silicon-containing material on the fin and providing the fin with a diamond-shaped cross-section and with an upper portion and a lower portion. The lower portion of the fin is covered with a masking layer. Further, a salicide layer is formed on the upper portion of the fin, and the masking layer prevents formation of the salicide layer on the lower portion of the fin.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 15, 2014
    Inventors: Hoong Shing Wong, Min-hwa Chi