Patents by Inventor Shinichi Watanabe

Shinichi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240125994
    Abstract: A light absorption anisotropic film that, when being applied to an image display device, it is easy to control a region where visibility is high and a region where visibility is low and viewing angle controllability is more excellent, an optical film, and an image display device. The light absorption anisotropic film contains a dichroic substance and a liquid crystal compound, in which the light absorption anisotropic film has a plurality of regions having different directions of transmittance central axes in an in-plane direction of the light absorption anisotropic film, in the plurality of regions, all angles ? between the transmittance central axes and a normal direction of a surface of the light absorption anisotropic film are in a range of 0° to 70°, and any of a specific requirement 1, a specific requirement 2, or a specific requirement 3 is satisfied.
    Type: Application
    Filed: December 4, 2023
    Publication date: April 18, 2024
    Applicant: FUJIFILM Corporation
    Inventors: Wataru HOSHINO, Shinichi YOSHINARI, Shinya WATANABE
  • Patent number: 11944468
    Abstract: A material decomposition apparatus for performing decomposition of a material in an object. The apparatus includes a data storage section for storing correction data preliminarily generated by decomposing one of three or more materials into the other two materials, a data input section to which radiation data of the object is inputted, the radiation data being divided into a plurality of energy levels, and a decomposition processing section for repeatedly performing two-material decomposition for decomposition of the other two materials of the three or more materials using the radiation data at different energy levels and the correction data to perform decomposition of the inside of the object into the three or more materials.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 2, 2024
    Assignee: FUJIFILM HEALTHCARE CORPORATION
    Inventors: Shinichi Kojima, Kazuma Yokoi, Isao Takahashi, Fumito Watanabe, Fuyuhiko Teramoto, Taiga Gotou
  • Publication number: 20240096357
    Abstract: According to one embodiment, a disk device includes a rotatable magnetic disk, an actuator which supports and moves a head, a ramp which holds the head at an unloaded position, a motor which rotates the magnetic disk, and a controller which performs a load operation and a seek operation. When a radial travel speed of the head during the load operation is referred to as Vr1, a circumferential travel speed of the head is referred to as Vt1, a radial travel speed of the head during the seek operation is referred to as Vrs, and a circumferential travel speed is referred to as Vts, the controller controls at least one of the radial travel speed of the head and number of revolutions of the magnetic disk to satisfy a relationship (Vr1/Vt1)<(Vrs/Vts).
    Type: Application
    Filed: February 15, 2023
    Publication date: March 21, 2024
    Inventors: Shinichi Kobatake, Toru Watanabe, Masami Yamane
  • Publication number: 20240084020
    Abstract: In one embodiment, the present disclosure provides pharmaceutical compositions for suppressing the progression of fibrosis in systemic sclerosis, which contain an antibody against IL-31 receptor A as an active ingredient. In another embodiment, the present disclosure provides pharmaceutical compositions for suppressing Th2 polarization to suppress the progression of fibrosis in systemic sclerosis, which comprise an antibody against IL-31 receptor A as an active ingredient. In a certain embodiment, the above-mentioned antibody is an antibody having a neutralizing activity against IL-31 receptor A.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 14, 2024
    Applicants: Maruho Co., Ltd., The University of Tokyo
    Inventors: Ayumi Yoshizaki, Ai Kuzumi, Shinichi Sato, Tomoyuki Fujita, Hideki Watanabe
  • Publication number: 20240069264
    Abstract: Provided is a laminate capable of reducing a change in hue of a reflected image in the surroundings (for example, window glass) from an original image, suppressing a hue shift of particularly the reflected image to redness, and suppressing the reflected image from being conspicuous, a reflection prevention system including this laminate, and an image display device including this laminate. The laminate includes a polarizer having an absorption axis in an in-plane direction, a light absorption anisotropic layer containing a liquid crystal compound and a dichroic substance, and a linear polarization conversion layer, in which an angle between a transmittance central axis of the light absorption anisotropic layer and a normal line of a layer plane of the light absorption anisotropic layer is 0° or greater and 45° or less.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Applicant: FUJIFILM Corporation
    Inventors: Shinichi YOSHINARI, Naoyoshi YAMADA, Naoya NISHIMURA, Shinya WATANABE, Naoya SHIBATA
  • Patent number: 11889212
    Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: January 30, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masayoshi Chiba, Shinichi Watanabe
  • Publication number: 20230209222
    Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 29, 2023
    Inventors: Masayoshi Chiba, Shinichi Watanabe
  • Patent number: 11606522
    Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: March 14, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masayoshi Chiba, Shinichi Watanabe
  • Publication number: 20220368843
    Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.
    Type: Application
    Filed: August 2, 2022
    Publication date: November 17, 2022
    Inventors: Masayoshi Chiba, Shinichi Watanabe
  • Patent number: 11462556
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 4, 2022
    Assignee: Kioxia Corporation
    Inventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
  • Patent number: 11438538
    Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: September 6, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masayoshi Chiba, Shinichi Watanabe
  • Patent number: 11283417
    Abstract: A decline in image quality that is caused by a variation of a gain in an amplification circuit is suppressed. The amplification circuit includes an amplification transistor, a cascode transistor, and a control circuit. The amplification transistor amplifies an input signal. The cascode transistor is configured to, in a case where a drain-source voltage between a drain and a source is higher than a predetermined voltage, supply a substantially-constant drain current to a reference potential line with a predetermined reference potential via the amplification transistor. Further, the control circuit is configured to, in a case where an initialization instruction is issued, control the drain-source voltage to be a value higher than the predetermined voltage.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: March 22, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shinichi Watanabe, Takehiro Otani
  • Publication number: 20210274117
    Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.
    Type: Application
    Filed: June 25, 2019
    Publication date: September 2, 2021
    Inventors: Masayoshi Chiba, Shinichi Watanabe
  • Publication number: 20210028185
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Application
    Filed: October 15, 2020
    Publication date: January 28, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
  • Publication number: 20210006212
    Abstract: A decline in image quality that is caused by a variation of a gain in an amplification circuit is suppressed. The amplification circuit includes an amplification transistor, a cascode transistor, and a control circuit. The amplification transistor amplifies an input signal. The cascode transistor is configured to, in a case where a drain-source voltage between a drain and a source is higher than a predetermined voltage, supply a substantially-constant drain current to a reference potential line with a predetermined reference potential via the amplification transistor. Further, the control circuit is configured to, in a case where an initialization instruction is issued, control the drain-source voltage to be a value higher than the predetermined voltage.
    Type: Application
    Filed: December 4, 2018
    Publication date: January 7, 2021
    Inventor: Shinichi Watanabe
  • Patent number: 10840257
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
  • Patent number: 10601379
    Abstract: A digital amplifier includes a digital PWM generator, a first amplifier circuit, a first low-pass filter, a second amplifier circuit, a second low-pass filter, an attenuator, an error extractor, an adder, and a voltage supply unit. The first amplifier circuit amplifies a digital PWM signal at a second voltage. The first low-pass filter extracts a low-frequency band voltage signal from the amplified digital PWM signal, and outputs the extracted voltage signal to a load. The second amplifier circuit amplifies the generated digital PWM signal at a third voltage. The error extractor extracts an error signal. The adder adds a digital error signal whose feedback gain is adjusted to a digital audio signal. The voltage supply unit generates the third voltage that has a voltage value of a predetermined ratio to a voltage value of the second voltage, and supplies the third voltage to the second amplifier circuit.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 24, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Shinichi Watanabe
  • Publication number: 20200066743
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Application
    Filed: February 11, 2019
    Publication date: February 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
  • Publication number: 20190028069
    Abstract: A digital amplifier includes a digital PWM generator, a first amplifier circuit, a first low-pass filter, a second amplifier circuit, a second low-pass filter, an attenuator, an error extractor, an adder, and a voltage supply unit. The first amplifier circuit amplifies a digital PWM signal at a second voltage. The first low-pass filter extracts a low-frequency band voltage signal from the amplified digital PWM signal, and outputs the extracted voltage signal to a load. The second amplifier circuit amplifies the generated digital PWM signal at a third voltage. The error extractor extracts an error signal. The adder adds a digital error signal whose feedback gain is adjusted to a digital audio signal. The voltage supply unit generates the third voltage that has a voltage value of a predetermined ratio to a voltage value of the second voltage, and supplies the third voltage to the second amplifier circuit.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 24, 2019
    Inventor: SHINICHI WATANABE
  • Patent number: D1019723
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: March 26, 2024
    Assignee: SUMITOMO ELECTRIC HARDMETAL CORP.
    Inventors: Takahiro Watanabe, Shinichi Maruyama, Norihisa Fujita, Hitoshi Tohkairin