Patents by Inventor Shinichi Watanabe
Shinichi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240125994Abstract: A light absorption anisotropic film that, when being applied to an image display device, it is easy to control a region where visibility is high and a region where visibility is low and viewing angle controllability is more excellent, an optical film, and an image display device. The light absorption anisotropic film contains a dichroic substance and a liquid crystal compound, in which the light absorption anisotropic film has a plurality of regions having different directions of transmittance central axes in an in-plane direction of the light absorption anisotropic film, in the plurality of regions, all angles ? between the transmittance central axes and a normal direction of a surface of the light absorption anisotropic film are in a range of 0° to 70°, and any of a specific requirement 1, a specific requirement 2, or a specific requirement 3 is satisfied.Type: ApplicationFiled: December 4, 2023Publication date: April 18, 2024Applicant: FUJIFILM CorporationInventors: Wataru HOSHINO, Shinichi YOSHINARI, Shinya WATANABE
-
Patent number: 11944468Abstract: A material decomposition apparatus for performing decomposition of a material in an object. The apparatus includes a data storage section for storing correction data preliminarily generated by decomposing one of three or more materials into the other two materials, a data input section to which radiation data of the object is inputted, the radiation data being divided into a plurality of energy levels, and a decomposition processing section for repeatedly performing two-material decomposition for decomposition of the other two materials of the three or more materials using the radiation data at different energy levels and the correction data to perform decomposition of the inside of the object into the three or more materials.Type: GrantFiled: May 18, 2020Date of Patent: April 2, 2024Assignee: FUJIFILM HEALTHCARE CORPORATIONInventors: Shinichi Kojima, Kazuma Yokoi, Isao Takahashi, Fumito Watanabe, Fuyuhiko Teramoto, Taiga Gotou
-
Publication number: 20240096357Abstract: According to one embodiment, a disk device includes a rotatable magnetic disk, an actuator which supports and moves a head, a ramp which holds the head at an unloaded position, a motor which rotates the magnetic disk, and a controller which performs a load operation and a seek operation. When a radial travel speed of the head during the load operation is referred to as Vr1, a circumferential travel speed of the head is referred to as Vt1, a radial travel speed of the head during the seek operation is referred to as Vrs, and a circumferential travel speed is referred to as Vts, the controller controls at least one of the radial travel speed of the head and number of revolutions of the magnetic disk to satisfy a relationship (Vr1/Vt1)<(Vrs/Vts).Type: ApplicationFiled: February 15, 2023Publication date: March 21, 2024Inventors: Shinichi Kobatake, Toru Watanabe, Masami Yamane
-
Publication number: 20240084020Abstract: In one embodiment, the present disclosure provides pharmaceutical compositions for suppressing the progression of fibrosis in systemic sclerosis, which contain an antibody against IL-31 receptor A as an active ingredient. In another embodiment, the present disclosure provides pharmaceutical compositions for suppressing Th2 polarization to suppress the progression of fibrosis in systemic sclerosis, which comprise an antibody against IL-31 receptor A as an active ingredient. In a certain embodiment, the above-mentioned antibody is an antibody having a neutralizing activity against IL-31 receptor A.Type: ApplicationFiled: November 29, 2021Publication date: March 14, 2024Applicants: Maruho Co., Ltd., The University of TokyoInventors: Ayumi Yoshizaki, Ai Kuzumi, Shinichi Sato, Tomoyuki Fujita, Hideki Watanabe
-
Publication number: 20240069264Abstract: Provided is a laminate capable of reducing a change in hue of a reflected image in the surroundings (for example, window glass) from an original image, suppressing a hue shift of particularly the reflected image to redness, and suppressing the reflected image from being conspicuous, a reflection prevention system including this laminate, and an image display device including this laminate. The laminate includes a polarizer having an absorption axis in an in-plane direction, a light absorption anisotropic layer containing a liquid crystal compound and a dichroic substance, and a linear polarization conversion layer, in which an angle between a transmittance central axis of the light absorption anisotropic layer and a normal line of a layer plane of the light absorption anisotropic layer is 0° or greater and 45° or less.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Applicant: FUJIFILM CorporationInventors: Shinichi YOSHINARI, Naoyoshi YAMADA, Naoya NISHIMURA, Shinya WATANABE, Naoya SHIBATA
-
Patent number: 11889212Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.Type: GrantFiled: February 22, 2023Date of Patent: January 30, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Masayoshi Chiba, Shinichi Watanabe
-
Publication number: 20230209222Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.Type: ApplicationFiled: February 22, 2023Publication date: June 29, 2023Inventors: Masayoshi Chiba, Shinichi Watanabe
-
Patent number: 11606522Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.Type: GrantFiled: August 2, 2022Date of Patent: March 14, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Masayoshi Chiba, Shinichi Watanabe
-
Publication number: 20220368843Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.Type: ApplicationFiled: August 2, 2022Publication date: November 17, 2022Inventors: Masayoshi Chiba, Shinichi Watanabe
-
Patent number: 11462556Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: GrantFiled: October 15, 2020Date of Patent: October 4, 2022Assignee: Kioxia CorporationInventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
-
Patent number: 11438538Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.Type: GrantFiled: June 25, 2019Date of Patent: September 6, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Masayoshi Chiba, Shinichi Watanabe
-
Patent number: 11283417Abstract: A decline in image quality that is caused by a variation of a gain in an amplification circuit is suppressed. The amplification circuit includes an amplification transistor, a cascode transistor, and a control circuit. The amplification transistor amplifies an input signal. The cascode transistor is configured to, in a case where a drain-source voltage between a drain and a source is higher than a predetermined voltage, supply a substantially-constant drain current to a reference potential line with a predetermined reference potential via the amplification transistor. Further, the control circuit is configured to, in a case where an initialization instruction is issued, control the drain-source voltage to be a value higher than the predetermined voltage.Type: GrantFiled: December 4, 2018Date of Patent: March 22, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Shinichi Watanabe, Takehiro Otani
-
Publication number: 20210274117Abstract: The present technology relates to a comparator that can easily modify operating point potential of the comparator, and an imaging device. A pixel signal output from a pixel, and, a reference signal with changeable voltage are input to a differential pair. A current mirror connected to the differential pair, and a voltage drop mechanism allowed to cause a predetermined voltage drop is connected between a transistor that configures the differential pair, and a transistor that configures the current mirror. A switch is connected in parallel to the voltage drop mechanism. The present technology can be applied, for example, to an image sensor that captures an image.Type: ApplicationFiled: June 25, 2019Publication date: September 2, 2021Inventors: Masayoshi Chiba, Shinichi Watanabe
-
Publication number: 20210028185Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: ApplicationFiled: October 15, 2020Publication date: January 28, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
-
Publication number: 20210006212Abstract: A decline in image quality that is caused by a variation of a gain in an amplification circuit is suppressed. The amplification circuit includes an amplification transistor, a cascode transistor, and a control circuit. The amplification transistor amplifies an input signal. The cascode transistor is configured to, in a case where a drain-source voltage between a drain and a source is higher than a predetermined voltage, supply a substantially-constant drain current to a reference potential line with a predetermined reference potential via the amplification transistor. Further, the control circuit is configured to, in a case where an initialization instruction is issued, control the drain-source voltage to be a value higher than the predetermined voltage.Type: ApplicationFiled: December 4, 2018Publication date: January 7, 2021Inventor: Shinichi Watanabe
-
Patent number: 10840257Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: GrantFiled: February 11, 2019Date of Patent: November 17, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
-
Patent number: 10601379Abstract: A digital amplifier includes a digital PWM generator, a first amplifier circuit, a first low-pass filter, a second amplifier circuit, a second low-pass filter, an attenuator, an error extractor, an adder, and a voltage supply unit. The first amplifier circuit amplifies a digital PWM signal at a second voltage. The first low-pass filter extracts a low-frequency band voltage signal from the amplified digital PWM signal, and outputs the extracted voltage signal to a load. The second amplifier circuit amplifies the generated digital PWM signal at a third voltage. The error extractor extracts an error signal. The adder adds a digital error signal whose feedback gain is adjusted to a digital audio signal. The voltage supply unit generates the third voltage that has a voltage value of a predetermined ratio to a voltage value of the second voltage, and supplies the third voltage to the second amplifier circuit.Type: GrantFiled: July 3, 2018Date of Patent: March 24, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Shinichi Watanabe
-
Publication number: 20200066743Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: ApplicationFiled: February 11, 2019Publication date: February 27, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
-
Publication number: 20190028069Abstract: A digital amplifier includes a digital PWM generator, a first amplifier circuit, a first low-pass filter, a second amplifier circuit, a second low-pass filter, an attenuator, an error extractor, an adder, and a voltage supply unit. The first amplifier circuit amplifies a digital PWM signal at a second voltage. The first low-pass filter extracts a low-frequency band voltage signal from the amplified digital PWM signal, and outputs the extracted voltage signal to a load. The second amplifier circuit amplifies the generated digital PWM signal at a third voltage. The error extractor extracts an error signal. The adder adds a digital error signal whose feedback gain is adjusted to a digital audio signal. The voltage supply unit generates the third voltage that has a voltage value of a predetermined ratio to a voltage value of the second voltage, and supplies the third voltage to the second amplifier circuit.Type: ApplicationFiled: July 3, 2018Publication date: January 24, 2019Inventor: SHINICHI WATANABE
-
Patent number: D1019723Type: GrantFiled: May 20, 2021Date of Patent: March 26, 2024Assignee: SUMITOMO ELECTRIC HARDMETAL CORP.Inventors: Takahiro Watanabe, Shinichi Maruyama, Norihisa Fujita, Hitoshi Tohkairin