Patents by Inventor Shinichiro Miyahara
Shinichiro Miyahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079492Abstract: A semiconductor device includes a second deep layer between a first deep layer and first current distribution layer and a base region in an active region and in a part of an inactive region adjacent to the active region. The second deep layer has a second stripe portion including lines connecting to the base region and the first deep layer. The semiconductor device further includes a second current distribution layer between the first current distribution layer and the base region and arranged between the lines of the second stripe portion. The first deep layer has a first stripe portion including a plurality of lines, and each line has an end portion connecting to a frame-shaped portion and an inner portion on an inner side of the end portion. The width of the end portion is equal to or greater than the inner portion.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Inventors: Atsuya AKIBA, Yuichi TAKEUCHI, Kazuki ARAKAWA, Yusuke HAYAMA, Yasushi URAKAMI, Shinichiro MIYAHARA, Tomoo MORINO
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Publication number: 20230197774Abstract: A semiconductor device includes a vertical semiconductor element having a deep layer, a current dispersion layer, a base region, a high-concentration region, and a trench gate structure. The deep layer has multiple sections being apart to each other in one direction. The current dispersion layer is between adjacent two of the sections of the deep layer. The high-concentration region is on a portion of the base region. The trench gate structure includes a gate trench, a gate insulation film and a gate electrode. The current dispersion layer is at a bottom of the trench gate structure, and has an ion-implanted layer extending from a bottom portion of the gate trench to a bottom portion of the deep layer or a location below the bottom portion of the deep layer.Type: ApplicationFiled: November 30, 2022Publication date: June 22, 2023Inventors: Shinichiro MIYAHARA, Shunsuke HARADA, Tomoo MORINO
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Publication number: 20220406932Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer, a base layer, a first electrode, and a second electrode. The substrate includes a cell region at which a semiconductor element is disposed and a temperature detection region at which a diode element is disposed. The first electrode is disposed at a side facing the substrate with the drift layer sandwiched between the substrate and the first electrode. The second electrode is disposed at a side facing the drift layer with the substrate sandwiched between the drift layer and the second electrode. The semiconductor element includes a first impurity region and a second impurity region disposed at a surface layer portion of the base layer. The diode element includes a first constituent layer at a surface layer portion of the base layer and a second constituent layer connected to the first constituent layer.Type: ApplicationFiled: June 14, 2022Publication date: December 22, 2022Inventors: Shinichiro Miyahara, Shoji Mizuno
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Patent number: 10784335Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.Type: GrantFiled: June 29, 2017Date of Patent: September 22, 2020Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuichi Takeuchi, Shinichiro Miyahara, Atsuya Akiba, Katsumi Suzuki, Yukihiko Watanabe
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Publication number: 20190386096Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.Type: ApplicationFiled: June 29, 2017Publication date: December 19, 2019Inventors: Yuichi TAKEUCHI, Shinichiro MIYAHARA, Atsuya AKIBA, Katsumi SUZUKI, Yukihiko WATANABE
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Patent number: 10181517Abstract: A silicon carbide single crystal includes: threading dislocations each of which having a dislocation line extending through a C-plane, and a Burgers vector including at least a component in a C-axis direction. In addition, a density of the threading dislocations having angles, each of which is formed by an orientation of the Burgers vector and an orientation of the dislocation line, larger than 0° and within 40° is set to 300 dislocations/cm2 or less. Furthermore, a density of the threading dislocations having the angles larger than 40° is set to 30 dislocations/cm2 or less.Type: GrantFiled: August 25, 2016Date of Patent: January 15, 2019Assignee: DENSO CORPORATIONInventors: Takeshi Okamoto, Hiroyuki Kondo, Takashi Kanemura, Shinichiro Miyahara, Yasuhiro Ebihara, Shoichi Onda, Hidekazu Tsuchida, Isaho Kamata, Ryohei Tanuma
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Patent number: 10153350Abstract: The bottom surface of the trench is provided so that a center part of the bottom surface protrudes upward with respect to a peripheral part of the bottom surface in a short direction. A thickness of the gate insulating film covering the peripheral part is thicker than a thickness of the gate insulating film covering the center part.Type: GrantFiled: August 3, 2015Date of Patent: December 11, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Jun Saito, Tatsuji Nagaoka, Sachiko Aoi, Yukihiko Watanabe, Shinichiro Miyahara, Takashi Kanemura
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Publication number: 20180286974Abstract: A provided method of manufacturing a semiconductor device includes formation of an interlayer insulating. The interlayer insulating film includes first and second insulating layers. The first insulating layer covers an upper surface of each of the gate electrodes. The second insulating layer is located on the first insulating layer. A contact hole is provided in the interlayer insulating film at a position between the trenches. Then the interlayer insulating film is heated at a temperature lower than the softening temperature of the first insulating layer and higher than the softening temperature of the second insulating layer so as to make a surface of the second insulating layer into a curved surface so that surfaces of end portions of the second insulating layer are sloping from the corresponding contact holes so as to be displaced upward toward a center of the corresponding trench.Type: ApplicationFiled: September 16, 2016Publication date: October 4, 2018Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Teruaki KUMAZAWA, Shinichiro MIYAHARA, Sachiko AOI
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Patent number: 10068972Abstract: A semiconductor device is provided with a semiconductor substrate and a trench gate. The semiconductor substrate is provided with a drift region of a first conductive type, wherein the drift region is in contact with the trench gate; a body region of a second conductive type, wherein the body region is disposed above the drift region and is in contact with the trench gate; a source region of the first conductive type, wherein the source region is disposed above the body region, exposed on the front surface of the semiconductor substrate and is in contact with the trench gate; and a front surface region of the second conductive type, wherein the front surface region is disposed above the source region, exposed on the front surface of the semiconductor substrate and is in contact with the trench gate.Type: GrantFiled: May 18, 2016Date of Patent: September 4, 2018Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Sachiko Aoi, Shoji Mizuno, Shinichiro Miyahara
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Publication number: 20180219069Abstract: A silicon carbide single crystal includes: threading dislocations each of which having a dislocation line extending through a C-plane, and a Burgers vector including at least a component in a C-axis direction. In addition, a density of the threading dislocations having angles, each of which is formed by an orientation of the Burgers vector and an orientation of the dislocation line, larger than 0° and within 40° is set to 300 dislocations/cm2 or less. Furthermore, a density of the threading dislocations having the angles larger than 40° is set to 30 dislocations/cm2 or less.Type: ApplicationFiled: August 25, 2016Publication date: August 2, 2018Inventors: Takeshi OKAMOTO, Hiroyuki KONDO, Takashi KANEMURA, Shinichiro MIYAHARA, Yasuhiro EBIHARA, Shoichi ONDA, Hidekazu TSUCHIDA, Isaho KAMATA, Ryohei TANUMA
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Patent number: 9972674Abstract: A technique stabilizing properties of SBDs is provided. An SBD is provided with a p-type contact region in contact with an anode electrode, and an n-type drift region in Schottky contact with the anode electrode. The p-type contact region includes a first p-type region having a corner portion, a second p-type region connected to the corner portion, and an edge filling portion located at a connection between the first p-type region and the second p-type region. First and second extended lines intersect at an acute angle, where the first extended line is a line extended from a contour of the first p-type region toward the connection and the second extended line is a line extended from a contour of the second p-type region toward the connection. An acute angle edge formed between the first extended line and the second extended line is filled with the edge filling portion.Type: GrantFiled: October 19, 2015Date of Patent: May 15, 2018Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Tatsuji Nagaoka, Hiroki Miyake, Shinichiro Miyahara, Sachiko Aoi
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Patent number: 9941366Abstract: Described herein is a semiconductor device comprising: a semiconductor substrate; a trench provided at a surface of the semiconductor substrate; a first insulating layer covering an inner surface of the trench; and a second insulating layer located at a surface of the first insulating layer in the trench. A refraction index of the first insulating layer is larger than a refraction index of the second insulating layer.Type: GrantFiled: October 14, 2014Date of Patent: April 10, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Atsushi Onogi, Shinichiro Miyahara
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Patent number: 9905686Abstract: In a plane view of the front surface of the semiconductor substrate, the source region and the first contact region are arranged adjacent to each other in a direction along the gate trench in an area being in contact with a side surface of the gate trench, and the second contact region is arranged adjacent to the source region and the first contact region in an area apart from the gate trench. The impurity concentration of the first contact region is lower than the impurity concentration of the second contact region.Type: GrantFiled: March 21, 2016Date of Patent: February 27, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masahiro Sugimoto, Yukihiko Watanabe, Shinichiro Miyahara
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Patent number: 9847414Abstract: A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench.Type: GrantFiled: November 16, 2015Date of Patent: December 19, 2017Assignee: Toyota Jidosha Kabushiki KaishaInventors: Hidefumi Takaya, Shinichiro Miyahara, Katsuhiro Kutsuki, Sachiko Aoi
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Publication number: 20170309716Abstract: A semiconductor device includes a semiconductor substrate in which a semiconductor element is provided and a covering insulation film provided on the semiconductor substrate. The semiconductor substrate includes a first portion and a second portion which has a thickness thinner than a thickness of the first portion. A step portion is provided at a part where the first portion and the second portion adjoin to each other. A corner member is provided at a corner between a side surface of the step portion and an upper surface of the second portion. An upper surface of the corner member slopes downward from the side surface of the step portion toward the second portion. The covering insulation film extends over from the first portion to the second portion, and covers the corner member.Type: ApplicationFiled: July 22, 2015Publication date: October 26, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Jun SAITO, Atsushi ONOGI, Sachiko AOI, Shinichiro MIYAHARA
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Publication number: 20170309717Abstract: The bottom surface of the trench is provided so that a center part of the bottom surface protrudes upward with respect to a peripheral part of the bottom surface in a short direction. A thickness of the gate insulating film covering the peripheral part is thicker than a thickness of the gate insulating film covering the center part.Type: ApplicationFiled: August 3, 2015Publication date: October 26, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Jun SAITO, Tatsuji NAGAOKA, Sachiko AOI, Yukihiko WATANABE, Shinichiro MIYAHARA, Takashi KANEMURA
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Patent number: 9793376Abstract: In a method of manufacturing a silicon carbide semiconductor device including a vertical switching element having a trench gate structure, with the use of a substrate having an off angle with respect to a (0001) plane or a (000-1) plane, a trench is formed from a surface of a source region to a depth reaching a drift layer through a base region so that a side wall surface of the trench faces a (11-20) plane or a (1-100) plane, and a gate oxide film is formed without performing sacrificial oxidation after formation of the trench.Type: GrantFiled: August 6, 2013Date of Patent: October 17, 2017Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shinichiro Miyahara, Toshimasa Yamamoto, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
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Publication number: 20170278923Abstract: A technique stabilizing properties of SBDs is provided. An SBD is provided with a p-type contact region in contact with an anode electrode, and an n-type drift region in Schottky contact with the anode electrode. The p-type contact region includes a first p-type region having a corner portion, a second p-type region connected to the corner portion, and an edge filling portion located at a connection between the first p-type region and the second p-type region. First and second extended lines intersect at an acute angle, where the first extended line is a line extended from a contour of the first p-type region toward the connection and the second extended line is a line extended from a contour of the second p-type region toward the connection. An acute angle edge formed between the first extended line and the second extended line is filled with the edge filling portion.Type: ApplicationFiled: October 19, 2015Publication date: September 28, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Tatsuji NAGAOKA, Hiroki MIYAKE, Shinichiro MIYAHARA, Sachiko AOI
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Publication number: 20170213907Abstract: High voltage-resistance of a switching device including a p-type region being in contact with a lower end of a bottom-insulating-layer is realized. The switching device includes a bottom-insulating-layer disposed at a bottom in a trench, and a gate electrode disposed on a front surface side of the bottom-insulating-layer. A semiconductor substrate includes a first n-type and p-type regions being in contact with the gate insulating film, a second p-type region being in contact with an end of the bottom-insulating-layer, and a second n-type region separating the second p-type region from the first p-type region. Distance A from a rear-surface-side-end of the first p-type region to a front-surface-side-end of the second p-type region, and distance B from a rear-surface-side-end of the-bottom-insulating layer to a rear-surface-side-end of the second p-type region satisfy A<4B.Type: ApplicationFiled: June 3, 2015Publication date: July 27, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Akitaka SOENO, Sachiko AOI, Shinichiro MIYAHARA
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Patent number: 9698017Abstract: A manufacturing method of a semiconductor device is provided by forming a trench in a surface of a SiC substrate, positioning a protective substrate to cover the trench, and annealing the SiC substrate and the protective substrate.Type: GrantFiled: February 29, 2016Date of Patent: July 4, 2017Assignee: Toyota Jidosha Kabushiki KaishaInventors: Tomoharu Ikeda, Shinichiro Miyahara, Sachiko Aoi