Patents by Inventor Shi-Ning Yang

Shi-Ning Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • APPARATUS AND METHOD CAPABLE OF SWITCHING DISPLAYED PICTURES
    Publication number: 20140089845
    Abstract: An apparatus capable of switching displayed pictures in response to a slide gesture by a user includes a display screen for displaying a zoomed in current picture, a touch determining unit, a picture processing unit, a control unit, a time calculating unit, and a calculating unit. The picture processing unit determines a width value of the current picture and a distance between a side of the current picture and an edge of the display screen adjacent to the side. The control unit controls the display screen to only display the target picture if a ratio of the distance to the width is equal to or greater than a predetermined ratio, and controls the display screen to only redisplay the current picture if a time duration of a slide gesture from beginning to ending is smaller than a predetermined time period. A related method is also provided.
    Type: Application
    Filed: January 5, 2013
    Publication date: March 27, 2014
    Inventors: HAI-SEN LIANG, CHIH-SAN CHIANG, SHI-NING YANG, XIANG HE, HUA-DONG CHENG
  • Guard wall to reduce delamination effects within a semiconductor die
    Patent number: 5986315
    Abstract: A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.
    Type: Grant
    Filed: August 26, 1993
    Date of Patent: November 16, 1999
    Assignee: Intel Corporation
    Inventors: Melton C. Bost, Robert A. Gasser, Shi-Ning Yang, Timothy L. Deeter
  • Via hole profile and method of fabrication
    Patent number: 5874358
    Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: February 23, 1999
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
  • Anchored via connection
    Patent number: 5619071
    Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
    Type: Grant
    Filed: August 15, 1995
    Date of Patent: April 8, 1997
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
  • Via hole profile and method of fabrication
    Patent number: 5470790
    Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: November 28, 1995
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-ning Yang, Peng Bai
  • Method of forming a guard wall to reduce delamination effects
    Patent number: 5270256
    Abstract: A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: December 14, 1993
    Assignee: Intel Corporation
    Inventors: Melton C. Bost, Robert A. Gasser, Shi-Ning Yang, Timothy L. Deeter