Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first electrode, a second electrode, a third electrode, a second magnetic portion, a first nonmagnetic portion, and a controller. The first magnetic portion includes an extension portion and a third portion. The extension portion includes a first portion and a second portion. The third portion is connected to the second portion. The first electrode is electrically connected to the first portion. At least a portion of the third portion is positioned between the second electrode and the third electrode. The second magnetic portion is provided between the second electrode and the at least a portion of the third portion. The first nonmagnetic portion is provided between the second magnetic portion and the at least a portion of the third portion. The controller is electrically connected to the first, second electrode, and third electrodes.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.

Abstract: According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-side current source, a negative-side current source, M cross switches, a coefficient memory unit, and a comparator. The positive-side current source is configured to output a first voltage corresponding to a value of 1/L of the current output from a positive-side terminal. The negative-side current source is configured to output a second voltage corresponding to a value of 1/L of the current output from a negative-side terminal. The memory unit includes M cells corresponding to the respective M coefficients. The comparator is configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage. Each M cell includes a first resistor and a second resistor.

Abstract: A semiconductor memory device includes a first and a second TFET whose gates and drains are cross-coupled. The drain of the first TFET is connected to a first node. The drain of the second TFET is connected to a second node. Included are a first access transistor connecting the first node to a first write bit line, a second access transistor connecting the second node to a second write bit line, and a third access transistor connecting the first node to a first read bit line. The first access transistor is constructed of a TFET connected in such a manner as that current flows from the first node to the first write bit line upon turning-on. The second access transistor is constructed of a TFET connected in such a manner as that current flows from the second node to the second write bit line upon turning-on.

Abstract: According to one embodiment, a semiconductor storage device includes a flip-flop circuit configured with two stages of inverters composed of TFETs. The flip-flop circuit includes first and second nodes. A first access transistor composed of a TFET is provided between the first node and a first write word-line. A second access transistor composed of a TFET is provided between the second node and a second write word-line. A MOS transistor which has a gate connected to the first node and responds to a voltage impressed on a read word-line to supply a voltage corresponding to a potential at the first node to a read bit-line is included. The first and second access transistors are configured with TFETs connected in a manner that a drain current flows from the first and second nodes to a write bit-line when turned on.

Abstract: According to one embodiment, a semiconductor memory device includes a source voltage adjustment circuit and a word line voltage adjustment circuit, which are configured to respectively supply a source voltage supply end and a word line switchingly with voltage-adjusted voltages, in response to a mode switching signal for switching between a retention state mode and an active state mode, wherein the source voltage supply end is connected to sources of MOS transistors forming a flip-flop of a memory cell, and the word line is connected to gates of access transistors.

Abstract: According to one embodiment, a semiconductor storage device includes a flip-flop circuit configured with two stages of inverters composed of TFETs The flip-flop circuit includes first and second nodes. A first access transistor composed of a TFET is provided between the first node and a first write word-line. A second access transistor composed of a TFET is provided between the second node and a second write word-line. A MOS transistor which has a gate connected to the first node and responds to a voltage impressed on a read word-line to supply a voltage corresponding to a potential at the first node to a read bit-line is included. The first and second access transistors are configured with TFETs connected in a manner that a drain current flows from the first and second nodes to a write bit-line when turned on.

Abstract: A semiconductor memory device includes a first and a second TFET whose gates and drains are cross-coupled. The drain of the first TFET is connected to a first node. The drain of the second TFET is connected to a second node. Included are a first access transistor connecting the first node to a first write bit line, a second access transistor connecting the second node to a second write bit line, and a third access transistor connecting the first node to a first read bit line. The first access transistor is constructed of a TFET connected in such a manner as that current flows from the first node to the first write bit line upon turning-on. The second access transistor is constructed of a TFET connected in such a manner as that current flows from the second node to the second write bit line upon turning-on.

Abstract: According to one embodiment, a semiconductor memory device includes a source voltage adjustment circuit and a word line voltage adjustment circuit, which are configured to respectively supply a source voltage supply end and a word line switchingly with voltage-adjusted voltages, in response to a mode switching signal for switching between a retention state mode and an active state mode, wherein the source voltage supply end is connected to sources of MOS transistors forming a flip-flop of a memory cell, and the word line is connected to gates of access transistors.

Abstract: A semiconductor device applies a hold voltage Vhold to an upper electrode of an electrostatic actuator and a ground voltage to a lower electrode. After the semiconductor device sets the voltage of the lower electrode to a test voltage Vtest, it eliminates the hold voltage Vhold from the upper electrode and places the voltage of the upper electrode in a high impedance state. The potential difference between the upper electrode and the lower electrode is set to Vhold?Vtest=Vmon. Thereafter, the voltage of the lower electrode is returned to the ground voltage. Whether the electrostatic actuator is placed in an open state or in a closed state is determined by measuring the capacitance between the electrodes based on the amount of drop of the voltage of the upper electrode due to capacitance coupling at the time.

Abstract: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

Abstract: A semiconductor device applies a hold voltage Vhold to an upper electrode of an electrostatic actuator and a ground voltage to a lower electrode. After the semiconductor device sets the voltage of the lower electrode to a test voltage Vtest, it eliminates the hold voltage Vhold from the upper electrode and places the voltage of the upper electrode in a high impedance state. The potential difference between the upper electrode and the lower electrode is set to Vhold?Vtest=Vmon. Thereafter, the voltage of the lower electrode is returned to the ground voltage. Whether the electrostatic actuator is placed in an open state or in a closed state is determined by measuring the capacitance between the electrodes based on the amount of drop of the voltage of the upper electrode due to capacitance coupling at the time.

Abstract: A semiconductor device applies a hold voltage Vhold to an upper electrode of an electrostatic actuator and a ground voltage to a lower electrode. After the semiconductor device sets the voltage of the lower electrode to a test voltage Vtest, it eliminates the hold voltage Vhold from the upper electrode and places the voltage of the upper electrode in a high impedance state. The potential difference between the upper electrode and the lower electrode is set to Vhold?Vtest=Vmon. Thereafter, the voltage of the lower electrode is returned to the ground voltage. Whether the electrostatic actuator is placed in an open state or in a closed state is determined by measuring the capacitance between the electrodes based on the amount of drop of the voltage of the upper electrode due to capacitance coupling at the time.

Abstract: A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

Abstract: When memory cells enter a data holding mode, a control circuit of a semiconductor memory device reads out a plurality of data from the memory cells to generate and store a check bit for error detection and correction, and performs a refresh operation in a period within an error occurrence allowable range of an error correcting operation performed by an ECC circuit by using the check bit. Before a normal operation mode is restored from the data holding mode, the control circuit performs control such that an error bit of the data is corrected by using the check bit. In an entry/exit period, read and write are performed by a page operation.

Abstract: When memory cells enter an operation mode which performs only data holding, a control circuit controls the memory cells and an ECC circuit as follows. A plurality of data are read out to generate and store a check bit for error detection and correction. Refreshing is performed in a period within the error occurrence allowable range of an error correcting operation performed by the ECC circuit by using the check bit. Before a normal operation mode is restored from the operation mode which performs only data holding, an error bit of the data is corrected by using the check bit. In an entry/exit period, read/write and an ECC operation are sequentially performed for all the memory cells by a page mode operation. Memory cells connected to a word line which is not accessed by the page mode operation are sequentially activated and refreshed.

Abstract: A semiconductor device applies a hold voltage Vhold to an upper electrode of an electrostatic actuator and a ground voltage to a lower electrode. After the semiconductor device sets the voltage of the lower electrode to a test voltage Vtest, it eliminates the hold voltage Vhold from the upper electrode and places the voltage of the upper electrode in a high impedance state. The potential difference between the upper electrode and the lower electrode is set to Vhold?Vtest=Vmon. Thereafter, the voltage of the lower electrode is returned to the ground voltage. Whether the electrostatic actuator is placed in an open state or in a closed state is determined by measuring the capacitance between the electrodes based on the amount of drop of the voltage of the upper electrode due to capacitance coupling at the time.

Abstract: A semiconductor memory device has a memory cell array in which a plurality of memory cells are arranged and operates in sync with a clock signal. A read and write operations are performed in the same cycle of the clock signal. The read operation allows the read column selection lines that have been designated by a first column address to connect the read data bus to the bit lines. The write operation allows the write column selection lines that have been designated by a second column address to connect the write data bus to the bit lines. Further, in the write operation, the data obtained by combining the data that has been error-corrected by the syndrome generation circuit and correction circuit with the data that has been input to the input circuit is coded by the code generation circuit and written in the memory cells.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a plurality of redundancy sections respectively provided for the plurality of memory blocks and configured to be substituted for defective memory cells, a test circuit that carries out a test on the memory cell array and outputs defective data, first and second memory circuit that temporarily store the defective data, a first write circuit that writes the defective data alternately in the first and second memory circuits, a first read circuit that reads the defective data alternately from the first and second memory circuits, a plurality of third memory circuits respectively provided for the plurality of memory blocks, that store the defective data, and a second write circuit that writes defective data read by the first read circuit in a third memory circuit corresponding to a memory block in which an error occurred.

Abstract: When memory cells enter a data holding mode, a control circuit of a semiconductor memory device reads out a plurality of data from the memory cells to generate and store a check bit for error detection and correction, and performs a refresh operation in a period within an error occurrence allowable range of an error correcting operation performed by an ECC circuit by using the check bit. Before a normal operation mode is restored from the data holding mode, the control circuit performs control such that an error bit of the data is corrected by using the check bit. In an entry/exit period, read and write are performed by a page operation.