Abstract: Even-numbered columns are arranged in the first memory cell array (bank), and odd-numbered columns are arranged in the second memory cell array (bank). A column address signal is input to an adder through a buffer. When data is read out of two or more columns, the adder generates a column address signal whose address value is more than that of the column address signal by one. The adder supplies a first column decoder with a column address signal for addressing an even-numbered column and supplies a second column decoder with a column address signal for addressing an odd-numbered column. Since the even-numbered columns and odd-numbered columns are arranged in their separate memory cell arrays, data read out of continuous two or more columns do not collide with each other.

Abstract: An LSI chip has a main surface occupied by a logic section, a data input/output section and a memory macro section. The memory macro section is a rectangular section arranged on the main surface of the LSI chip. A test control circuit is arranged along one side of the memory macro section. A data input/output circuit is arranged along another side of the memory macro section. The test control circuit may be arranged along one side of the LSI chip. Test data is supplied from the test control circuit to the data input/output circuit through a data bus. As a result, a load of designing a memory logic LSI can be lightened.

Abstract: When data stored in a memory cell of a memory cell array is written into cache memory, a write signal LW is set at an "H" level. The write signal LW is input into a data-line pair initialization select circuit via an initialization control circuit, and a signal EQE is set at an "H" level in all columns. A data-line pair initialization circuit then sets the potential of the data-line pairs in all columns at the same level. When the write signal LW is input to a transfer gate via a transfer gate control circuit, the transfer gates in all columns are turned ON. The delay time of the transfer gate control circuit is the same as or greater than the delay time of the initialization control.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of pairs of bit lines to each of which the plurality of memory cells arranged in the column direction are connected, a plurality of latch type amplifiers each of which is provided between the bit lines of a corresponding one of the bit line pairs to amplify a potential difference between the bit lines, a plurality of activation circuits for respectively activating the plurality of latch type amplifiers, a data bus acting as passages of input data, a plurality of latch type storage circuits each of which is provided on a corresponding one of the columns and connected to the data bus, for temporarily storing the input data, a plurality of transfer gates for transferring the input data from the latch type storage circuits to the latch type amplifiers, and a transfer control circuit for controlling the transfer gates to simultaneously transfer the input data from the latch type s

Abstract: A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of pairs of bit lines to each of which the plurality of memory cells arranged in the column direction are connected, a plurality of latch type amplifiers each of which is provided between the bit lines of a corresponding one of the bit line pairs to amplify a potential difference between the bit lines, a plurality of activation circuits for respectively activating the plurality of latch type amplifiers, a data bus acting as passages of input data, a plurality of latch type storage circuits each of which is provided on a corresponding one of the columns and connected to the data bus, for temporarily storing the input data, a plurality of transfer gates for transferring the input data from the latch type storage circuits to the latch type amplifiers, and a transfer control circuit for controlling the transfer gates to simultaneously transfer the input data from the latch type s

Abstract: A semiconductor device of a memory-macro type can be designed within a short time to have a desired storage capacity, which does not occupy a large area, so as to reduce the chip cost. The semiconductor device includes a memory macro having sub-memory macros, each sub-memory macro having a DRAM memory-cell array, and a row decoder and a column decoder for selecting any desired memory-cell from the memory cell of the array. The memory macro also includes a control-section macro having a DC potential generating circuit for generating various DC potentials required to drive the sub-memory macros. At least one of the sub-memory macros is combined with the control-section macro to form the memory macro as a one-chip memory capable of storing an integral multiple of N bits.

Abstract: A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate.

Abstract: A data register that stores the data corresponding to the selected memory cell in a memory cell array is provided near the memory cell array. A decoder that selects the data from the data register starts decoding in response to an address signal accessing the memory cells in synchronization with a clock signal determining the operation period. In the first half of an operation period of the clock signal, the decoder outputs a signal in response to a signal corresponding to the address signal determined in the preceding operation period. According to the output of the decoder, the data register is selected. In the latter half of the operation period, a signal corresponding to a new address signal for the next operation period is transferred to the decoder. By doing this, the output control signal in the decoder is caused to synchronize with a signal driving an address signal, enabling the proper address to be selected without fail.

Abstract: According to the present invention, a data bus common to a plurality of memory cell arrays is formed by selecting a column so as to prevent a data collision from occurring. Specifically, two memory cell arrays have each of data buses in common. A column decoder is supplied with a control signal to control a column selection logic circuit. The column selection logic circuit is so controlled that the data read out to the data buses in response to the control signal is prevented from colliding with each other during the simultaneous access to the two cell arrays.

Abstract: A semiconductor memory device comprises column decoders of the number greater than the number of column addresses of a memory cell array and logical circuits of the same number as that of the column addresses. A column gate of a column is controlled by means of a logical OR between outputs from a plurality of column decoders for decoding different column addresses. As a result, even a column located at an end of the memory cell array can be accessed by means of a logical OR between outputs from a column decoder corresponding to the column and another column decoder.

Abstract: A semiconductor memory device comprises a plurality of memory cells including at least a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell and paired with the first bit line, an equalizer connected between the first and second bit lines, an amplifier connected between the first and second bit lines, a first driving signal line connected to the amplifier and drives the amplifier, a second driving signal line connected to the amplifier and paired with the first driving signal line, a driver for driving the amplifier and connected to the first and second driving signal lines and containing a precharger for presetting the potentials of the first and second driving signal lines to a predetermined precharge potential and a driving signal supply circuit for supplying a driving signal to the first and second driving signal lines, and a control circuit for controlling the equalizer and the driver, wherein the control c

Abstract: A semiconductor memory device includes a sense amplifier which senses data read out from a memory cell, a transfer gate coupled to an output of the sense amplifier, and a data latch circuit coupled to the transfer gate. The data latch circuit includes two MOS transistors of a same conductivity type connected in series between a pair of I/O data lines. The gates of the two MOS transistors are cross-coupled to the data lines respectively, thereby enabling a rapid data transfer between the memory cell and a data bus.

Abstract: An improved field-effect transistor (FET) using compound semiconductors is provided. The improved FET includes a reverse-conduction type semiconductor layer formed on a one-conduction type semiconductor layer. The reverse-conduction type semiconductor layer has a thickness smaller than that of the one-conduction type semiconductor layer and an impurity concentration lower than that of the same. The FET further includes an intrinsic semiconductor layer formed on the reverse conduction type semiconductor layer, and a Schottky junction gate electrode formed on the intrinsic semiconductor layer. The FET also includes a channel constituted by a potential well developed at the interface between the intrinsic semiconductor layer and the reverse-conduction type semiconductor layer.