Patents by Inventor Shinji Mori
Shinji Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958355Abstract: An accelerator pedal system includes a pedal lever, a lock mechanism, an actuator, and an ECU. The pedal lever operates according to a step-on operation. The lock mechanism can restrict an operation of the pedal lever. The actuator switches between a locked state in which the operation of the pedal lever is restricted by the lock mechanism and an unlocked state in which the operation of the pedal lever is not restricted. The ECU includes a lock operation determination unit and an actuator control unit. The lock operation determination unit unlocks the pedal lever when an approaching object from behind is detected during a travel of a vehicle in the locked state.Type: GrantFiled: August 23, 2022Date of Patent: April 16, 2024Assignee: DENSO CORPORATIONInventors: Soichi Kinouchi, Yuusuke Yoshida, Takuto Kita, Hideyuki Mori, Shinji Komatsu
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Publication number: 20240099975Abstract: An object of the present invention is to provide an anti-tumor agent that exhibits a remarkably excellent anti-tumor effect. According to the present invention, there is provided an anti-tumor agent for curing cancer, the anti-tumor agent having a liposome which has an inner water phase and having an aqueous solution which is an outer water phase and disperses the liposome, in which the liposome encompasses topotecan or a salt thereof, a lipid constituting the liposome contains a lipid modified with polyethylene glycol, dihydrosphingomyelin, and cholesterol, the inner water phase contains an ammonium salt, and the topotecan or the salt thereof encompassed in the liposome is administered at a dose rate of 0.1 mg/m2 body surface area to 10 mg/m2 body surface area, in terms of topotecan per administration.Type: ApplicationFiled: November 22, 2023Publication date: March 28, 2024Applicant: FUJIFILM CorporationInventors: Susumu SHIMOYAMA, Keiko SUZUKI, Mikinaga MORI, Takeshi MATSUMOTO, Shinji NAKAYAMA, Yasushi MOROHASHI, Toshifumi KIMURA
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Patent number: 11938815Abstract: An accelerator pedal system includes a pedal lever configured to perform an operation in accordance with a step-on operation, a lock mechanism configured to restrict the operation of the pedal lever, and an actuator configured to switch between a locked state in which the operation of the pedal lever is restricted by the lock mechanism and an unlocked state in which the operation of the pedal lever is free from restriction by the lock mechanism. In the accelerator pedal system, a controller configured to change an energization amount to the actuator when a disturbance is detected during a vehicle traveling in the locked state. Thus, the lock state can be suitably controlled.Type: GrantFiled: August 23, 2022Date of Patent: March 26, 2024Assignee: DENSO CORPORATIONInventors: Soichi Kinouchi, Yuusuke Yoshida, Takuto Kita, Hideyuki Mori, Shinji Komatsu
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Publication number: 20240097044Abstract: According to one embodiment, a semiconductor device includes a first conductive layer between first and second insulating layers with an oxide semiconductor column extending in the first direction through these layers. A third insulating layer covers the column. The column has a first semiconductor portion at a first position matching the first insulating layer, a second semiconductor portion at a second position matching second insulating layer, and a third semiconductor portion at a third position matching the first conductive layer. The first semiconductor portion is continuous along a second direction between the third insulating layer, the second semiconductor portion is continuous along the second direction between the third insulating layer, but the third semiconductor portion is not continuous between the third insulating layer.Type: ApplicationFiled: August 25, 2023Publication date: March 21, 2024Inventors: Yusuke KASAHARA, Kappei IMAMURA, Akifumi GAWASE, Shinji MORI, Akihiro KAJITA
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Patent number: 11844219Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.Type: GrantFiled: June 30, 2022Date of Patent: December 12, 2023Assignee: KIOXIA CORPORATIONInventors: Yuta Saito, Shinji Mori, Keiichi Sawa, Kazuhisa Matsuda, Kazuhiro Matsuo, Hiroyuki Yamashita
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Patent number: 11785774Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.Type: GrantFiled: April 20, 2022Date of Patent: October 10, 2023Assignee: KIOXIA CORPORATIONInventors: Keiichi Sawa, Kazuhiro Matsuo, Kazuhisa Matsuda, Hiroyuki Yamashita, Yuta Saito, Shinji Mori, Masayuki Tanaka, Kenichiro Toratani, Atsushi Takahashi, Shouji Honda
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Publication number: 20230309310Abstract: A semiconductor device of embodiments includes: a semiconductor layer containing silicon (Si); a first insulating layer provided in a first direction of the semiconductor layer; a second insulating layer surrounded by the semiconductor layer in a first cross section perpendicular to the first direction and containing silicon (Si) and oxygen (O); a third insulating layer surrounded by the second insulating layer in the first cross section and containing a metal element and oxygen (O); and a conductive layer surrounded by the first insulating layer in a second cross section perpendicular to the first direction, provided in the first direction of the third insulating layer, and spaced from the semiconductor layer.Type: ApplicationFiled: September 9, 2022Publication date: September 28, 2023Applicant: Kioxia CorporationInventors: Yuta SAITO, Shinji MORI, Hiroyuki YAMASHITA, Satoshi NAGASHIMA, Kazuhiro MATSUO, Kota TAKAHASHI, Shota KASHIYAMA, Keiichi SAWA, Junichi KANEYAMA
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Patent number: 11751397Abstract: In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.Type: GrantFiled: June 27, 2022Date of Patent: September 5, 2023Assignee: Kioxia CorporationInventors: Yuta Saito, Shinji Mori, Atsushi Takahashi, Toshiaki Yanase, Keiichi Sawa, Kazuhiro Matsuo, Hiroyuki Yamashita
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Patent number: 11647628Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer; first and second insulating layers in contact with the first semiconductor layer; a second semiconductor layer in contact with the first insulating layer; a third semiconductor layer in contact with the second insulating layer; a first conductor; a third insulating layer in contact with the first conductor; a fourth insulating layer provided between the second semiconductor layer and the third insulating layer; a first charge storage layer provided between the second semiconductor layer and the fourth insulating layer; and a fifth insulating layer provided between the second semiconductor layer and the first charge storage layer. The second semiconductor layer, the first conductor, the third to fifth insulating layers, and the first charge storage layer function as a first memory cell.Type: GrantFiled: September 10, 2020Date of Patent: May 9, 2023Assignee: Kioxia CorporationInventors: Yuta Saito, Shinji Mori, Keiji Hosotani, Daisuke Hagishima, Atsushi Takahashi
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SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Publication number: 20230090044Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, a first oxide semiconductor layer between the first electrode and the second electrode, the first oxide semiconductor layer containing in, Zn, and a first metal element, and the first metal element being at least one metal of Ga, Mg, or Mn, a second oxide semiconductor layer between the first oxide semiconductor layer and the second electrode, the second oxide semiconductor layer containing In, Zn, and the first metal element, a third oxide semiconductor layer between the first oxide semiconductor layer and the second oxide semiconductor layer, the third oxide semiconductor layer containing in, Zn, and a second metal element, the second metal element being at least one metal of Al, Hf, La, Sn, Ta, Ti, W, Y, or Zr, a gate electrode facing the third oxide semiconductor layer, and a gate insulating.Type: ApplicationFiled: March 4, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventors: Tomoki ISHIMARU, Shinji MORI, Kazuhiro MATSUO, Keiichi SAWA, Kenichiro TORATANI -
Publication number: 20230048781Abstract: A method for manufacturing a semiconductor device of an embodiment includes: forming a first film on a semiconductor layer containing silicon (Si), the first film containing a metal element and oxygen (O) and having a first thickness; and forming a second film between the semiconductor layer and the first film using radical oxidation, the second film containing silicon (Si) and oxygen (O) and having a second thickness larger than the first thickness.Type: ApplicationFiled: March 15, 2022Publication date: February 16, 2023Applicant: Kioxia CorporationInventors: Yuta SAITO, Shinji MORI, Hiroyuki YAMASHITA
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Publication number: 20220352188Abstract: A semiconductor memory device includes a first semiconductor layer, first conductive layers, electric charge accumulating portions, a first conductivity-typed second semiconductor layer, a first wiring, a second conductivity-typed third semiconductor layer, and a second conductive layer. The first semiconductor layer extends in a first direction. First conductive layers are arranged in the first direction and extend in a second direction. Electric charge accumulating portions are disposed between the first semiconductor layer and first conductive layers. The second semiconductor layer is connected to one end of the first semiconductor layer. The first wiring is connected to the first semiconductor layer via the second semiconductor layer. The third semiconductor layer is connected to a side surface in a third direction of the first semiconductor layer. The second conductive layer extends in the second direction and is connected to the first semiconductor layer via the third semiconductor layer.Type: ApplicationFiled: March 11, 2022Publication date: November 3, 2022Applicant: Kioxia CorporationInventors: Ryo FUKUOKA, Fumitaka ARAI, Kouji MATSUO, Hiroaki KOSAKO, Keiji HOSOTANI, Takayuki KAKEGAWA, Shinya NAITO, Shinji MORI
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Publication number: 20220336493Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Applicant: Kioxia CorporationInventors: Yuta SAITO, Shinji MORI, Keiichi SAWA, Kazuhisa MATSUDA, Kazuhiro MATSUO, Hiroyuki YAMASHITA
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Publication number: 20220336492Abstract: In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.Type: ApplicationFiled: June 27, 2022Publication date: October 20, 2022Applicant: KIOXIA CORPORATIONInventors: Yuta SAITO, Shinji MORI, Atsushi TAKAHASHI, Toshiaki YANASE, Keiichi SAWA, Kazuhiro MATSUO, Hiroyuki YAMASHITA
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Publication number: 20220310640Abstract: A semiconductor storage device includes a first conductive layer that extends in a first direction; a second conductive layer that extends in the first direction and is arranged with the first conductive layer in a second direction; a first insulating layer that is provided between the first conductive layer and the second conductive layer; a semiconductor layer that extends in the second direction and faces the first conductive layer, the second conductive layer, and the first insulating layer in a third direction; a first charge storage layer that is provided between the first conductive layer and the semiconductor layer; a second charge storage layer that is provided between the second conductive layer and the semiconductor layer; a first high dielectric constant layer that is provided between the first conductive layer and the first charge storage layer; and a second high dielectric constant layer provided between the second conductive layer and the second charge storage layer.Type: ApplicationFiled: August 30, 2021Publication date: September 29, 2022Applicant: Kioxia CorporationInventors: Natsuki FUKUDA, Ryota NARASAKI, Takashi KURUSU, Yuta KAMIYA, Kazuhiro MATSUO, Shinji MORI, Shoji HONDA, Takafumi OCHIAI, Hiroyuki YAMASHITA, Junichi KANEYAMA, Ha HOANG, Yuta SAITO, Kota TAKAHASHI, Tomoki ISHIMARU, Kenichiro TORATANI
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Publication number: 20220302162Abstract: According to one embodiment, a semiconductor storage device includes a plurality of electrode films on a substrate, spaced from one another in a first direction. A charge storage film is provided on a side face the electrode films via a first insulating film. A semiconductor film is provided on a side face of the charge storage film via a second insulating film. The charge storage film includes a plurality of insulator regions contacting the first insulating film, a plurality of semiconductor or conductor regions provided between the insulator regions and another insulator region.Type: ApplicationFiled: August 26, 2021Publication date: September 22, 2022Inventors: Hiroyuki Yamashita, Yuta Saito, Keiichi Sawa, Kazuhiro Matsuo, Yuta Kamiya, Shinji Mori, Kota Takahashi, Junichi Kaneyama, Tomoki Ishimaru, Kenichiro Toratani, Ha Hoang, Shouji Honda, Takafumi Ochiai
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Publication number: 20220301896Abstract: A substrate processing apparatus includes a chamber, a supply pipe, a discharge pipe, a trap section, a heater, a buffer section, and a cooling pipe. The chamber houses a substrate. The supply pipe supplies a processing gas into the chamber. The discharge pipe discharges a gas produced in the chamber. The trap section is disposed in the discharge pipe. The heater heats the trap section. The buffer section is disposed downstream of the trap section in the discharge pipe. The cooling pipe cools the buffer section.Type: ApplicationFiled: August 20, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Yoshinori TOKUDA, Toshiaki YANASE, Shinji MORI
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Publication number: 20220262954Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, a first metallic region provided between the first electrode and the second electrode and includes at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), magnesium (Mg), manganese (Mn), titanium (Ti), tungsten (W), molybdenum (Mo), and tin (Sn), a second metallic region provided between the first metallic region and the second electrode and includes the at least one metallic element, a semiconductor region provided between the first metallic region and the second metallic region and includes the at least one metallic element and oxygen (O), an insulating region provided between the first metallic region and the second metallic region and is surrounded by the semiconductor region, a gate electrode surrounding the semiconductor region, and a gate insulating layer provided between the semiconductor region and the gate electrode.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Applicant: Kioxia CorporationInventors: Tomoki ISHIMARU, Shinji MORI, Kazuhiro MATSUO, Keiichi SAWA, Akifumi GAWASE
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Publication number: 20220246640Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Applicant: KIOXIA CORPORATIONInventors: Keiichi SAWA, Kazuhiro MATSUO, Kazuhisa MATSUDA, Hiroyuki YAMASHITA, Yuta SAITO, Shinji MORI, Masayuki TANAKA, Kenichiro TORATANI, Atsushi TAKAHASHI, Shouji HONDA
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Patent number: 11404437Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.Type: GrantFiled: August 14, 2020Date of Patent: August 2, 2022Assignee: KIOXIA CORPORATIONInventors: Yuta Saito, Shinji Mori, Keiichi Sawa, Kazuhisa Matsuda, Kazuhiro Matsuo, Hiroyuki Yamashita