Patents by Inventor Shinji Mori

Shinji Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190371810
    Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.
    Type: Application
    Filed: February 25, 2019
    Publication date: December 5, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta SAITO, Shinji MORI, Keiichi SAWA, Kazuhisa MATSUDA, Kazuhiro MATSUO, Hiroyuki YAMASHITA
  • Publication number: 20190361365
    Abstract: Provided is an electrophotographic photosensitive member that suppresses image smearing at the time of its repeated use, and expresses satisfactory wear resistance and electric characteristics. The electrophotographic photosensitive member includes a support and a photosensitive layer in the stated order, wherein a surface layer of the electrophotographic photosensitive member contains a copolymer of a hole-transportable compound having a chain-polymerizable functional group and a specific compound having maleimide groups.
    Type: Application
    Filed: May 20, 2019
    Publication date: November 28, 2019
    Inventors: Haruki Mori, Koichi Nakata, Masaki Nonaka, Shinji Takagi
  • Publication number: 20190360350
    Abstract: A steam turbine includes a rotating shaft (1); a rotor blade (4) having a platform (43) and a rotor blade main body (40); a casing (2); a stationary blade (7) having a stationary blade main body (70) and a stator shroud (71); and a projecting portion (45A) that projects from the platform (43) toward a upstream side in a central axis direction (Da). The projecting portion (45A) has, on a side thereof facing a radially inner side, a guide surface (45f) that gradually inclines or curves radially inward from a base end portion (45s) on the platform (43) side to a tip end portion (45t) on an upstream side in the central axis direction (Da).
    Type: Application
    Filed: February 16, 2018
    Publication date: November 28, 2019
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Masataka Mori, Shinji Fukao, Hideaki Sugishita, Kazuyuki Matsumoto, Yoshihiro Kuwamura
  • Patent number: 10488769
    Abstract: Provided is an electrophotographic photosensitive member, wherein a surface layer of the electrophotographic photosensitive member contains a copolymer of a hole-transportable compound having a polymerizable functional group and a compound represented by the following general formula (1).
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: November 26, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichi Nakata, Shinji Takagi, Haruki Mori, Masaki Nonaka, Shubun Kujirai
  • Patent number: 10488771
    Abstract: A surface layer of an electrophotographic photosensitive member contains a cured product of a composition containing a hole transport compound having an acryloyloxy group or a methacryloyloxy group, and a compound having a specific structure.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: November 26, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Haruki Mori, Masaki Nonaka, Koichi Nakata, Shinji Takagi
  • Patent number: 10481514
    Abstract: An image forming apparatus includes a latent image bearer, an electrostatic latent image forming device, a potential sensor, a toner image forming device, a toner adhesion amount detector, and circuitry. The circuitry controls the electrostatic latent image forming device to create an adjustment pattern on the latent image bearer when the image forming apparatus is not printing, controls the potential sensor to detect an electric potential of the adjustment pattern, controls the electrostatic latent image forming device and the toner image forming device to create a test toner image during a printing period, controls the toner adhesion amount detector to detect a toner adhesion amount of the test toner image, and adjusts at least one image forming condition of the electrostatic latent image forming device and the toner image forming device based on the electric potential of the adjustment pattern and the toner adhesion amount of the test toner image.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: November 19, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Atsushi Mori, Hideo Muroi, Makoto Komatsu, Shinji Kato
  • Patent number: 10451984
    Abstract: A coating film of a coating liquid for a surface layer, the coating liquid containing a hole transporting compound having a chain-polymerizable functional group and a compound having a specified structure, is cured to thereby form a surface layer of an electrophotographic photosensitive member.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: October 22, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Haruki Mori, Masaki Nonaka, Shinji Takagi, Koichi Nakata
  • Patent number: 10396280
    Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Shinji Mori, Masayuki Tanaka, Kazuhiro Matsuo, Kenichiro Toratani, Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Yuta Saito
  • Patent number: 10395813
    Abstract: The present invention provides a magnetic core which can be produced with improved productivity without increasing a material cost and has required magnetic and mechanical properties and a process for producing the same. The magnetic core is produced by compression molding and thereafter thermally hardening iron-based soft magnetic powder having resin films formed on surfaces of particles thereof. The resin film is an uncured resin film formed by dry mixing the iron-based soft magnetic powder and epoxy resin containing a latent curing agent with each other at a temperature not less than a softening temperature of the epoxy resin and less than a thermal curing starting temperature thereof. The iron-based soft magnetic powder having the resin films formed on the surfaces of the particles thereof is compression molded by using a die to produce a compression molded body.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 27, 2019
    Assignee: NTN CORPORATION
    Inventors: Ikuo Uemoto, Shinji Miyazaki, Takuji Harano, Natsuhiko Mori, Hiroyuki Noda
  • Patent number: 10312199
    Abstract: A manufacturing method of a semiconductor device includes preparing a wiring substrate including a first surface, a plurality of first terminals formed on the first surface, and a second surface opposite to the first surface, arranging a first adhesive on the first surface of the wiring substrate, and after the arranging of the first adhesive, mounting a first semiconductor chip, which includes a first front surface, a plurality of first front electrodes formed on the first front surface, a first rear surface opposite to the first front surface, a plurality of first rear electrodes formed on the first rear surface, and a plurality of through electrodes electrically connecting the plurality of first front electrodes to the plurality of first rear electrodes, on the first surface of the wiring substrate via the first adhesive.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: June 4, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Watanabe, Tsuyoshi Kida, Yoshihiro Ono, Kentaro Mori, Kenji Sakata, Yusuke Yamada
  • Patent number: 10310395
    Abstract: Provided are an electrophotographic photosensitive member capable of satisfying abrasion resistance and electrical properties and suppressing image deletion, and an electrophotographic apparatus and a process cartridge having the electrophotographic photosensitive member. A surface layer of the electrophotographic photosensitive member contains a polymer of a hole transport material having a polymerizable functional group, wherein the hole transport material has a specific structure.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: June 4, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichi Nakata, Haruki Mori, Shinji Takagi, Masaki Nonaka, Ryoichi Tokimitsu
  • Patent number: 10304850
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, a stacked body provided on the substrate, a plurality of electrode films being stacked to be separated from each other in the stacked body, a semiconductor pillar piercing the plurality of electrode films, a first insulating film provided between the semiconductor pillar and the electrode films, a second insulating film provided between the semiconductor pillar and the first insulating film; and a third insulating film provided between the first insulating film and the electrode films. The first insulating film includes silicon, nitrogen, oxygen, and carbon.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Shinji Mori, Kenichiro Toratani
  • Patent number: 10286661
    Abstract: Disclosed is a liquid discharge method of discharging liquid with a liquid discharge head having a heating surface that contacts and heats the liquid and a discharge port that faces the heating surface and discharges the liquid. The method includes heating the liquid through the heating surface to generate a bubble such that the bubble communicates with an atmosphere, thereby discharging the liquid. The liquid that is being discharged from the discharge port includes a trailing portion. The trailing portion moves toward the heating surface in response to a reduction in volume of the bubble and contacts the heating surface. The method further includes heating the trailing portion through the heating surface while the trailing portion is in contact with the heating surface, thereby generating a bubble.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 14, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shintaro Kasai, Yoshiyuki Nakagawa, Akira Shibasaki, Masataka Sakurai, Ken Tsuchii, Akiko Hammura, Tatsurou Mori, Shinji Kishikawa
  • Patent number: 10283646
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second gate electrode layers, an inter-layer insulating layer, a channel layer, a tunneling insulating layer, first and second charge storage portions, and a blocking insulating layer. The channel layer is separated from the first and second gate electrode layers, and the inter-layer insulating layer. The tunneling insulating layer is provided between the first gate electrode layer and the channel layer. The first charge storage portion is provided between the first gate electrode layer and the tunneling insulating layer. The second charge storage portion is provided the second gate electrode layer and the tunneling insulating layer. The blocking insulating layer is provided between the inter-layer insulating layer and the tunneling insulating layer, between the first gate electrode layer and the first charge storage portion, between the inter-layer insulating layer and the first charge storage portion.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: May 7, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Keiichi Sawa, Shinji Mori, Masayuki Tanaka, Kenichiro Toratani, Takashi Furuhashi
  • Publication number: 20190081144
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a columnar portion. The columnar portion is provided within the stacked body, and includes a semiconductor portion extended in the first direction and a charge storage layer provided between the plural electrode films and the semiconductor portion. The columnar portion has a first region between the plural electrode films and the charge storage layer, a second region in which the charge storage layer is provided, and a third region between the semiconductor portion and the charge storage layer. The columnar portion includes impurities within the first region, the second region, and the third region. An average impurity concentration of the second region is higher than an average impurity concentration of the third region. An average impurity concentration of the third region is higher than an average impurity concentration of the first region.
    Type: Application
    Filed: March 2, 2018
    Publication date: March 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsunori ISOGAI, Shinji MORI
  • Publication number: 20190027538
    Abstract: In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.
    Type: Application
    Filed: February 8, 2018
    Publication date: January 24, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Takaumi Morita, Masayuki Tanaka, Shinji Mori, Kazuhiro Matsuo, Yuta Saito, Kenichiro Toratani, Hisashi Okuchi
  • Publication number: 20180277757
    Abstract: A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including(a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shinji MORI, Masayuki TANAKA, Kazuhiro MATSUO, Kenichiro TORATANI, Keiichi SAWA, Kazuhisa MATSUDA, Atsushi TAKAHASHI, Yuta SAITO
  • Publication number: 20180261445
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: carrying a substrate alternately stacked an electrode layer and an insulation layer into a chamber; increasing the temperature in the chamber to a predetermined temperature; and supplying hydrogen and material gas including metal simultaneously into the chamber, and supplying oxidizing gas the partial pressure ratio of which to the hydrogen is set so as to provide an atmosphere of reducing the electrode layer, by using an ALD method, and thereby forming, on a surface of the electrode layer and a surface of the insulation layer, a metal oxide layer obtained by oxidizing the metal.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 13, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi FURUHASHI, Masayuki Tanaka, Shinji Mori, Kenichiro Toratani
  • Patent number: 10043864
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a first electrode. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode opposes the third semiconductor layer. An orientation ratio of the third semiconductor layer is higher than an orientation ratio of the first semiconductor layer.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 7, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Minoru Oda, Shinji Mori, Kiwamu Sakuma, Masumi Saitoh
  • Patent number: 10020364
    Abstract: One embodiment includes: forming a laminated body by alternately laminating a conducting layer and an interlayer insulating layer on a substrate; forming a memory hole passing through the laminated body; forming a memory gate insulating layer including a charge storage layer on an inner wall of the memory hole; forming a first semiconductor layer on the memory gate insulating layer; forming a cover film on the first semiconductor layer; removing the memory gate insulating layer, the first semiconductor layer, and the cover film on a bottom surface of the memory hole, to expose the substrate; forming an epitaxial layer on the exposed substrate; removing the cover film; and forming the second semiconductor layer along the first semiconductor layer, to electrically couple: the substrate to the first semiconductor layer; and the substrate to the second semiconductor layer, via the epitaxial layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Yamasaki, Makoto Fujiwara, Shinji Mori