Patents by Inventor Shinji Tanaka

Shinji Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190151418
    Abstract: Provided is a means effective in bone regeneration or bone augmentation. Provided is a porous composite containing octacalcium phosphate and parathyroid hormone.
    Type: Application
    Filed: February 24, 2017
    Publication date: May 23, 2019
    Applicant: TOYOBO CO., LTD.
    Inventors: Shinji Kamakura, Satoru Nakajou, Atsushi Iwai, Fumihiko Kajii, Hidenori Tanaka, Kazuo Sasaki
  • Patent number: 10297788
    Abstract: A light emitting apparatus (10) includes a substrate (100), an insulating layer (160), a light emitting element (102), a coating film (140), and a structure (150). The insulating layer (160) is formed over one surface of the substrate (100), and includes an opening (162). The light emitting element (102) is formed in the opening (162). The coating film (140) is formed over the one surface of the substrate (100), and covers a portion of the light emitting element (102), the insulating layer (160), and the one surface of the substrate (100). The coating film (140) does not cover another portion of the substrate (100) (for example, a portion of an end portion: hereinafter, referred to as a first portion). The structure (150) is located between the first portion of the substrate (100) and the insulating layer (160). The coating film (140) also covers the insulating layer (160).
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 21, 2019
    Assignees: PIONEER CORPORATION, TOHOKU PIONEER CORPORATION
    Inventors: Koji Fujita, Shinsuke Tanaka, Yuji Saito, Shinji Nakajima
  • Patent number: 10283194
    Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 7, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Yabuuchi, Shinji Tanaka
  • Publication number: 20190122703
    Abstract: A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
  • Publication number: 20190092741
    Abstract: An object of the present invention is to provide a compound having an anti-inflammatory activity or a pharmacologically acceptable salt thereof. The solution of the present invention is a compound of general formula (1) or a pharmacologically acceptable salt thereof. wherein the symbols in the formula are defined below: R1: e.g., a C1-C6 alkyl group; R2: a C1-C6 alkyl group; A: e.g., an oxygen atom; and R3: e.g., a C1-C6 alkyl group.
    Type: Application
    Filed: March 29, 2017
    Publication date: March 28, 2019
    Applicant: Daiichi Sankyo Company, Limited
    Inventors: Keiji Saito, Katsuyoshi Nakajima, Toru Taniguchi, Osamu Iwamoto, Satoshi Shibuya, Yasuyuki Ogawa, Kazumasa Aoki, Nobuya Kurikawa, Shinji Tanaka, Momoko Ogitani, Eriko Kioi, Kaori Ito, Natsumi Nishihama, Tsuyoshi Mikkaichi, Wataru Saitoh
  • Patent number: 10210947
    Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Sano, Shunya Nagata, Shinji Tanaka
  • Patent number: 10197011
    Abstract: The present embodiment improves the durability of an afterburner and yet suppresses a reduction in the engine efficiency of an aircraft engine. A ring-shaped cooling channel through which cooling air flows is formed between the outer peripheral surface of a liner and the inner peripheral surface of a rear duct. A plurality of cooling holes for blowing the cooling air along the inner peripheral surface of the liner are formed penetrating the liner. A ring-shaped annulus flame-holding member on the inner peripheral surface of the liner is provided concentrically with respect to a plurality of radial flame-holding members. The inner diameter of the annulus flame-holding member decreases in the downstream direction. The annulus flame-holding member functions as a throttle ring which throttles the flowing of a main flow of a mixed gas inside the liner.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 5, 2019
    Assignee: IHI Corporation
    Inventors: Shinji Tanaka, Katsuyoshi Takahashi, Jun Hosoi
  • Patent number: 10195162
    Abstract: The present invention provides a tolterodine-containing patch in which an adhesive layer is laminated on a backing, characterized in that the adhesive layer is obtainable by adding tolterodine to an adhesive base comprising a rubber adhesive, a tackifier resin, and a softener, wherein the tolterodine is present in the form of a free base in the adhesive base.
    Type: Grant
    Filed: December 25, 2012
    Date of Patent: February 5, 2019
    Assignee: TEIKOKU SEIYAKU CO., LTD.
    Inventors: Taiki Shibata, Kensuke Murata, Kenichi Hattori, Shinji Tanaka
  • Patent number: 10170161
    Abstract: A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data, and reading the data written into the memory cells.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: January 1, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
  • Patent number: 10168050
    Abstract: The present embodiment sufficiently ensures the ignition stability and the flame-holding property of an afterburner while suppressing a reduction in the efficiency of an aircraft engine. A flame holder is disposed directly downstream of an injection hole of a fuel injector in a liner. The flame holder comprises: a ring-shaped annulus flame-holding member which is provided on the inner circumferential surface of the liner and is capable of propagating a flame in the circumferential direction; and a plurality of radial flame-holding members which are radially disposed inwards of the annulus flame-holding member and are capable of propagating the flame in the radial direction. A guide ring is provided inwards of the radial flame-holding members, and a ring-shaped guide channel that guides a fuel-containing mixed gas in the downstream direction is formed between the outer peripheral surface of the guide ring and the inner peripheral surface of the annulus flame-holding member.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 1, 2019
    Assignee: IHI Corporation
    Inventors: Shinji Tanaka, Katsuyoshi Takahashi, Jun Hosoi
  • Publication number: 20180366184
    Abstract: A semiconductor storage device includes a plurality of memory cells arranged in a matrix, a word line provided corresponding to a memory cell row, a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which the word line is formed, a word driver circuit configured to drive the word line, and a dummy word driver circuit configured to increase voltage on the word line based on interline capacitance between the word line and the dummy word line.
    Type: Application
    Filed: November 14, 2016
    Publication date: December 20, 2018
    Inventors: Yuichiro ISHII, Shinji TANAKA
  • Publication number: 20180352348
    Abstract: A bone conduction device includes: a case; a vibrating body disposed in the case; and a first weight held by the vibrating body vibrating body. The vibrating body includes a support portion supported by the case and a first holding portion that holds the first weight. A center of mass of the first weight is located outside a first normal region of the vibrating body in the first holding portion.
    Type: Application
    Filed: June 6, 2017
    Publication date: December 6, 2018
    Applicant: Sonitus Technologies Inc.
    Inventors: Munenori AOYAGI, Hirohiko OOWAKI, Shinji TANAKA, Michael PARE, Tim PROULX
  • Publication number: 20180340978
    Abstract: An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.
    Type: Application
    Filed: March 8, 2018
    Publication date: November 29, 2018
    Inventors: Makoto YABUUCHI, Shinji TANAKA
  • Publication number: 20180342308
    Abstract: A semiconductor device is comprised of a memory cell array with multiple memory cells arranged in a matrix, multiple bit-line pairs provided for each memory cell column in the memory cell array, multiple input/output circuits provided respectively corresponding to the multiple bit-line pairs, and as interface control circuit that controls the data input/output to the multiple input/output circuits when performing the data write and data read for each memory cell row in a normal mode. The interface control circuit is comprised of a selection circuit. When the data write and data read are performed for each memory cell row in a test mode, the selection circuit selects the data input/output to one of first input/output circuit and a second input/output circuit, respectively corresponding to a first memory cell included in the memory cell row and a second memory cell adjoining the first memory cell, according to a test address.
    Type: Application
    Filed: April 9, 2018
    Publication date: November 29, 2018
    Applicant: Renesas Electronics Corporation
    Inventor: Shinji TANAKA
  • Patent number: 10138339
    Abstract: The present invention provides a film for a solar cell back sheet including: a substrate film; a white layer on at least one surface of the substrate film; and an adhesive protective layer, the white layer being formed by applying an aqueous composition for the white layer including a white pigment, a first aqueous binder and an inorganic oxide filler to at least one surface of the substrate film, and the adhesive protective layer being formed by applying an aqueous composition for the adhesive protective layer including a second aqueous binder, and which has excellent production efficiency, a white pigment uniformly present in the layers, and excellent adhesiveness between the respective layers, and a producing method of the film for a solar cell back sheet.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: November 27, 2018
    Assignee: FUJIFILM Corporation
    Inventor: Shinji Tanaka
  • Patent number: 10120960
    Abstract: A device arrangement rule generation unit generates device arrangement rules each including a past installation space of devices and relative direction information indicating a relative direction between devices that were arranged in the past installation space. An input unit inputs information on a new installation space and devices to be arranged in the new installation space. A device arrangement rule extraction unit extracts device arrangement rules each including the devices to be arranged in the new installation space input by the input unit. A device arrangement calculation unit calculates an arrangement position of the devices to be arranged in the new installation space based on relative direction information included in one of the device arrangement rules extracted by the device arrangement rule extraction unit and based on dimensions of the devices to be arranged in the new installation space input by the input unit.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: November 6, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Reiko Inoue, Takaharu Matsui, Shinji Tanaka, Kenji Kondo
  • Publication number: 20180315471
    Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 1, 2018
    Inventors: Makoto YABUUCHI, Shinji TANAKA
  • Publication number: 20180261280
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Application
    Filed: May 16, 2018
    Publication date: September 13, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Shinji TANAKA, Makoto YABUUCHI, Yuta YOSHIDA
  • Publication number: 20180240513
    Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.
    Type: Application
    Filed: April 19, 2018
    Publication date: August 23, 2018
    Inventors: Toshiaki SANO, Ken SHIBATA, Shinji TANAKA, Makoto YABUUCHI, Noriaki MAEDA
  • Patent number: 10049723
    Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: August 14, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Yabuuchi, Shinji Tanaka