Abstract: Disclosed is a semiconductor structure including a semiconductor substrate including an electronic circuit, which is provided in a predetermined region of the semiconductor substrate; a wall which is formed to encircle the predetermined region of the semiconductor substrate; a wiring provided in a region of the semiconductor substrate outside of the predetermined region of the semiconductor substrate; an external connection electrode provided on the wiring; a sealing resin which seals the wiring, the sealing resin being filled in the region of the semiconductor substrate outside of the wall; and a transparent resin to seal the predetermined region of the semiconductor substrate, the transparent resin being filled inside of the wall.

Abstract: A dummy columnar electrode having the same outer size and cross section as a columnar electrode formed in a semiconductor device formation region is formed in the peripheral part of a semiconductor device test region in the same process as the columnar electrode. The semiconductor device test regions are provided at several places on the peripheral edge of an effective semiconductor wafer region. Each of the semiconductor device test regions is formed to partly protrude out of the effective semiconductor wafer region. Thus, the number of the semiconductor device formation regions to be products can be prevented from decreasing.

Abstract: A semiconductor device comprises a semiconductor construct including a semiconductor substrate, and an external connection electrode provided to protrude on the surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including the side surface of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.

Abstract: A wafer process material is prepared which has a plurality of semiconductor formation regions of different planar sizes, each including a low dielectric constant film/wiring line stack structure component. A laser beam is applied onto a dicing street of the necessary semiconductor formation region and onto its straight extension in order to remove partial areas of the low dielectric constant film/wiring line stack structure components of the necessary semiconductor formation region and the unnecessary semiconductor formation region so that first groove and the second groove are formed. A protective film is formed in the second groove formed in the unnecessary semiconductor formation region and on the low dielectric constant film/wiring line stack structure component. An upper wiring line and a sealing film are formed on the protective film, and a semiconductor wafer is cut along the dicing street.

Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.

Abstract: A network electronic component comprises a network-electronic-component substrate, a thin-film passive element provided on the substrate, and a plurality of external connection electrodes provided on the substrate in connection with the thin-film passive element.

Abstract: Disclosed is a semiconductor device manufacturing method including: preparing a semiconductor wafer which includes a semiconductor device forming region surrounded by dicing streets extending along first and second directions and including columnar electrodes and a sealing film; with respect to the columnar electrodes nearest the dicing streets in the first direction or the columnar electrodes nearest the dicing streets in the second direction, solder paste layers are displaced to an inward side of the semiconductor device forming region; by performing reflow, allowing the solder paste layer contacting with the columnar electrodes nearest the pair of dicing streets extending in the first direction or the solder paste layer contacting with the columnar electrodes nearest the pair of dicing streets extending in the second direction to move so as to form solder bumps.

Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.

Abstract: In the manufacture of a semiconductor, in unnecessary semiconductor device formation areas 22b and 22c, a columnar electrode 14 made of copper is formed only in an area excluding an area corresponding to a dicing street 23 and both sides of the dicing street 23, and is not formed in the area corresponding to the dicing street 23 and both sides of the dicing street 23. As a result, the dicing blade is prevented from being clogged with copper. In this case, a plurality of layers of low-dielectric film and the same number of layers of wiring are formed on a semiconductor wafer such that they are alternately laminated, and the columnar electrode is formed on a connection pad portion of upper layer wiring formed on the low-dielectric film wiring laminated structure section with an insulating film therebetween.

Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.

Abstract: A semiconductor package includes at least one semiconductor constructing body which has a semiconductor substrate and a plurality of external connection electrodes formed thereon. An insulating film covers the semiconductor constructing body. Each of interconnections which has a projecting electrode is formed on the insulating film. The projecting electrodes of the interconnection cut through the insulating film at portions corresponding to the external connection electrodes and electrically connected to the external connection electrodes.

Abstract: A wafer process material is prepared which has a plurality of semiconductor formation regions of different planar sizes, each including a low dielectric constant film/wiring line stack structure component. A laser beam is applied onto a dicing street of the necessary semiconductor formation region and onto its straight extension in order to remove partial areas of the low dielectric constant film/wiring line stack structure components of the necessary semiconductor formation region and the unnecessary semiconductor formation region so that first groove and the second groove are formed. A protective film is formed in the second groove formed in the unnecessary semiconductor formation region and on the low dielectric constant film/wiring line stack structure component. An upper wiring line and a sealing film are formed on the protective film, and a semiconductor wafer is cut along the dicing street.

Abstract: The semiconductor device of the present invention has a semiconductor substrate having a top surface of a quadrangular shape on which a plurality of connection pads are formed, an insulation film formed on the semiconductor substrate except the connection pads, and a plurality of external connection electrodes formed on the insulation film so as to be connected to the connection pads. The plurality of external connection electrodes constitute at least a first group of external connection electrodes which are arranged on first lines running along each of the two diagonal lines of the semiconductor substrate and second group of external connection electrodes which are arranged on second lines running along the first lines outside the first lines as seen from the diagonal lines.

Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.

Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.

Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.

Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.

Abstract: A semiconductor package includes at least one semiconductor constructing body which has a semiconductor substrate and a plurality of external connection electrodes formed thereon. An insulating film covers the semiconductor constructing body. Each of interconnections which has a projecting electrode is formed on the insulating film. The projecting electrodes of the interconnection cut through the insulating film at portions corresponding to the external connection electrodes and electrically connected to the external connection electrodes.

Abstract: A semiconductor package includes at least one semiconductor constructing body which has a semiconductor substrate and a plurality of external connection electrodes formed thereon. An insulating film covers the semiconductor constructing body. Each of interconnections which has a projecting electrode is formed on the insulating film. The projecting electrodes of the interconnection cut through the insulating film at portions corresponding to the external connection electrodes and electrically connected to the external connection electrodes.