Patents by Inventor Shinji Yuasa

Shinji Yuasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070258170
    Abstract: A single-crystalline MgO (001) substrate 11 is prepared, and then an epitaxial Fe (001) lower electrode (first electrode) 17 with a thickness of 50 nm is grown on a MgO (001) seed layer 15 at room temperature. Annealing is then performed in ultrahigh vacuum (2×10?8 Pa) at 350° C. A 2-nm thick MgO (001) barrier layer 21 is epitaxially grown on the Fe (001) lower electrode (first electrode) 17 at room temperature, using electron beam evaporation of MgO. A Fe (001) upper electrode (second electrode) 23 with a thickness of 10 nm is then grown on the MgO (001) barrier layer 21 at room temperature, successively followed by the deposition of a IrMn layer 25 with a thickness of 10 nm on the Fe (001) upper electrode (second electrode) 23. The IrMn layer 25 is used for realizing an antiparallel magnetization alignment by giving an exchange-biasing field to the upper electrode 23.
    Type: Application
    Filed: August 11, 2005
    Publication date: November 8, 2007
    Inventor: Shinji Yuasa
  • Publication number: 20070195592
    Abstract: The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared by the following steps. A single-crystalline MgO(001) substrate 11 is prepared. An epitaxial Fe(001) lower electrode (a first electrode) 17 with the thickness of 50 nm is grown on a MgO(001) seed layer 15 at room temperature, followed by annealing under ultrahigh vacuum (2×10?8 Pa) and at 350° C. A MgO(001) barrier layer 21 with the thickness of 2 nm is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) with the thickness of 10 nm is then formed on the MgO(001) barrier layer 21 at room temperature. This is successively followed by the deposition of a Co layer 21 with the thickness of 10 nm on the Fe(001) upper electrode (the second electrode) 23.
    Type: Application
    Filed: March 10, 2005
    Publication date: August 23, 2007
    Inventor: Shinji Yuasa
  • Publication number: 20070128470
    Abstract: By varying only the thickness of a known material having superior magnetic characteristics to increase spin polarization without changing the chemical composition, a tunnel magnetoresistive element capable of producing a larger magnetoresistive effect is provided. The tunnel magnetoresistive element includes an underlayer (nonmagnetic or antiferromagnetic metal film); an ultrathin ferromagnetic layer disposed on the underlayer; an insulating layer disposed on the ultrathin ferromagnetic layer; and a ferromagnetic electrode disposed on the insulating layer.
    Type: Application
    Filed: February 12, 2007
    Publication date: June 7, 2007
    Applicants: National Inst. of Advanced Ind. Science and Tech., JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Taro Nagahama, Shinji Yuasa, Yoshishige Suzuki
  • Patent number: 7220498
    Abstract: By varying only the thickness of a known material having superior magnetic characteristics to increase spin polarization without changing the chemical composition, a tunnel magnetoresistive element capable of producing a larger magnetoresistive effect is provided. The tunnel magnetoresistive element includes an underlayer (nonmagnetic or antiferromagnetic metal film); an ultrathin ferromagnetic layer disposed on the underlayer; an insulating layer disposed on the ultrathin ferromagnetic layer; and a ferromagnetic electrode disposed on the insulating layer.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: May 22, 2007
    Assignees: National Institute of Advanced Industrial Science and Technology, Japan Science and Technology Agency
    Inventors: Taro Nagahama, Shinji Yuasa, Yoshishige Suzuki
  • Patent number: 7095657
    Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: August 22, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Inc.
    Inventors: Yoshinori Takase, Hideaki Kurata, Keiichi Yoshida, Ken Matsubara, Michitaro Kanamitsu, Shinji Yuasa
  • Publication number: 20060176735
    Abstract: The MR ratio of an MTJ device is increased. A single-crystalline MgO (001) substrate 11 is prepared, and then an epitaxial Fe (001) lower electrode (first electrode) 17 with a thickness of 50 nm is grown on a MgO (001) seed layer 15 at room temperature. Annealing is then performed in ultrahigh vacuum (2×10?8 Pa) at 350° C. A 2-nm thick MgO (001) barrier layer 21 is epitaxially grown on the Fe (001) lower electrode (first electrode) 17 at room temperature, using electron beam evaporation of MgO. A Fe (001) upper electrode (second electrode) 23 with a thickness of 10 nm is then grown on the MgO (001) barrier layer 21 at room temperature, which is successively followed by the deposition of a Co layer 21 with a thickness of 10 nm on the Fe (001) upper electrode (second electrode) 23. The Co layer 21 is used for realizing an antiparallel magnetization alignment by enhancing an exchange bias magnetic field of the upper electrode 23.
    Type: Application
    Filed: October 27, 2005
    Publication date: August 10, 2006
    Inventor: Shinji Yuasa
  • Publication number: 20060056115
    Abstract: A magnetoresistance effect device including a multilayer structure having a pair of ferromagnetic layers and a barrier layer positioned between them, wherein at least one ferromagnetic layer has at least the part contacting the barrier layer made amorphous and the barrier layer is an MgO layer having a highly oriented texture structure.
    Type: Application
    Filed: September 7, 2005
    Publication date: March 16, 2006
    Applicants: ANELVA Corporation, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: David Djayaprawira, Koji Tsunekawa, Motonobu Nagai, Hiroki Maehara, Shinji Yamagata, Naoki Watanabe, Shinji Yuasa
  • Publication number: 20060007737
    Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.
    Type: Application
    Filed: September 14, 2005
    Publication date: January 12, 2006
    Inventors: Yoshinori Takase, Hideaki Kurata, Keiichi Yoshida, Ken Matsubara, Michitaro Kanamitsu, Shinji Yuasa
  • Patent number: 6958940
    Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: October 25, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Takase, Hideaki Kurata, Keiichi Yoshida, Ken Matsubara, Michitaro Kanamitsu, Shinji Yuasa
  • Publication number: 20050095769
    Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.
    Type: Application
    Filed: February 28, 2002
    Publication date: May 5, 2005
    Inventors: Yoshinori Takase, Hideaki Kurata, Keiichi Yoshida, Ken Matsubara, Michitaro Kanamitsu, Shinji Yuasa
  • Publication number: 20040144995
    Abstract: By varying only the thickness of a known material having superior magnetic characteristics to increase spin polarization without changing the chemical composition, a tunnel magnetoresistive element capable of producing a larger magnetoresistive effect is provided.
    Type: Application
    Filed: November 26, 2003
    Publication date: July 29, 2004
    Inventors: Taro Nagahama, Shinji Yuasa, Yoshishige Suzuki
  • Patent number: 6710986
    Abstract: There is proposed a high-sensitive TMR element wherein the selection of electronic state contributing to tunnel conduction is optimized. In this invention, a junction plane between a ferromagnetic layer (210) having a bcc structure and a tunnel barrier layer (310) is constituted by (211) plane or (110) plane of the ferromagnetic layer (210). The tunnel barrier layer (310) is formed of a thin aluminum oxide film which is formed through two stages, i.e. a first stage wherein an aluminum film having a thickness of 1 nm or less is formed on the surface of a magnetic metal by taking advantage of the excellent wettability of aluminum to the surface of metallic film, the resultant aluminum film being subsequently naturally oxidized or oxidized by oxygen radical; and a second stage wherein an aluminum thin film is formed directly from an aluminum flux in an oxygen atmosphere or an atmosphere of oxygen radical.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: March 23, 2004
    Assignees: Hitachi, Ltd., Agency of Industrial Science and Technology
    Inventors: Toshihiko Sato, Shinji Yuasa