Abstract: Fixed-length data (560) contained in a database (560) are segmented into a number of pieces of data that are searchable at a time and searching is performed at high speed. As means for it, a pointer table (500), a secondary pointer table, a local table, and a fixed-length-data table are provided, and when more segmentation is required, a table having a numeric-value comparing function is further provided. As means for performing efficient configuration/management of the tables and for performing management that does not interfere with a search operation, an empty-house table (700), an empty-room table (720), a room-management table (740), and a structure-management table (760) may be provided.

Abstract: A motor control circuit includes: a detector outputting a detection signal in accordance with the motor rpm; a counter counting the number of clocks in accordance with a rotational cycle represented by the detection signal; a controller counting a DC motor based on the count value; and a divider dividing a frequency of a basic clock based on a preset division value to generate a counting clock. The divider generates a counting clock having a frequency corresponding to a rotational cycle, and the counter counts the number of counting clocks.

Abstract: Upon implementing a data registration into or a data retrieval from a data table (3) where first item data are registered along with corresponding second item data, there are used a first pointer table (1) where pointers to part of the registered data in the data table are registered in storage positions that are designated by hash values obtained by applying a first hash function (6) to the first item data of the part of the registered data, and a second pointer table (2) where pointers to the other registered data in the data table are registered in storage positions that are designated by hash values obtained by applying a second hash function (22) to the first item data of the other registered data.

Abstract: To provide a DRAM that reduces access latency during refresh and performs refresh for any non-accessed bank in parallel with normal memory accesses. Furthermore, the DRAM allows access to a bank that is undergoing refresh. The DRAM includes a circuit for directing refresh execution by comparing bank address of both access and refresh operations, a circuit for specifying a bank address of the memory cells to be refreshed, a circuit for addressing a row address of the memory cells to be refreshed in the specified bank, a means for refreshing the memory cells, and a means for accessing the memory cells directly after refresh without denying the access request.

Abstract: The present invention discloses a memory, and a refresh method for memory, which performs a normal access and refresh one after another within one operation cycle of SRAM. The memory of the present invention comprises a refresh enable which directs execution of refresh, a row address counter that addresses a row address of memory cells to be refreshed, and an execution circuit which refreshes the memory cells of the addressed row address in response to the direction of execution of refresh.

Abstract: The present invention relates to a DRAM having a memory array that is divided into a plurality of memory blocks. A memory block having a long data retention time is selected from the plurality of memory blocks and a logical address is allocated to the selected memory block. The selected memory block is refreshed at longer time intervals compared to conventional DRAMs resulting in lower power consumption.

Abstract: When an output of data is switched from a memory to a memory controller, the memory controller takes in write data output from the memory, and outputs the write data taken in to a data bus. Subsequently, the memory controller outputs read data taken thereinto to the data bus, and then outputs write data of its own to the data bus.

Abstract: A DRAM and access method for DRAM with a high data rate in a random row access mode. The DRAM includes a plurality of memory blocks composed of a plurality of storage segments each with a series of main word lines and sub-word lines. Each memory block is decoded into multiple segments and the main word lines are activated to select a predetermined number of sub-word lines. A corner block is provided that contains a plurality of Z-lines for selecting one of the sub-wordlines and a plurality of segment select lines for selecting a specific memory segment by activating a local Z-line.

Abstract: A distributor and a search controller are added to the memory. A search is performed with an algorithm such as quick search by repeating reading of memory cells, comparing of the reading result, and narrowing down of entries to be compared based on the comparison result. Performing this sequential processing in the memory provides valid data in a bus time plus about half of a cycle time required in repeating reading a conventional memory. Then, the latter half of the cycle time can be used for comparison, as well as generation of the next memory cell address, so that the search can be finished in a bus time multiplied by the number of repetitions of reading the memory cells plus one bus time. As a result, a CAM function can be achieved that allows for more than tens of thousands of entry data items, the number of which is equal to the size of DRAM divided by the number of banks, rather than hundreds or thousands of entry data items as conventional CAM.

Abstract: The object of this invention is to provide a timing circuit that can change a clock period with low power consumption. The timing circuit includes a clock generator 11, comparators 12 and 13 for comparing an inputted control voltage TDV and reference voltages VR, respectively, retaining circuits 18 and 19 for retaining outputs of the comparators, respectively, and circuits 20, 21 and 22 for producing timing pulses TDT as an output thereof based on outputs of the retaining circuits and clock signals outputted from the clock generator. Each comparator receives a first clock signal SS outputted from the clock generator and is operated only for a time corresponding to a short pulse width of the first clock signal SS.

Abstract: The object of this invention is to provide a timing circuit that can change a clock period with low power consumption. The timing circuit includes a clock generator 11, comparators 12 and 13 for comparing an inputted control voltage TDV and reference voltages VR, respectively, retaining circuits 18 and 19 for retaining outputs of the comparators, respectively, and circuits 20, 21 and 22 for producing timing pulses TDT as an output thereof based on outputs of the retaining circuits and clock signals outputted from the clock generator. Each comparator receives a first clock signal SS outputted from the clock generator and is operated only for a time corresponding to a short pulse width of the first clock signal SS.

Abstract: A communication control apparatus and method for improving the search process for determining a transfer route for a packet received based on search information is described. The search information is associated with a tree structure. A mask prefix is associated with at least one entry, each entry including information on the mask length of a mask prefix associated therewith and a sort key. Each entry is assigned to a node in the tree structure according to a sorting order. Each node is linked to a different node at the next lower hierarchy via a branch based on the entry of the node. An extracting means 26 extracts a destination address of the packet received. Search means 27 searches a search target node 28 specified by a search control means 29 for an entry having information on best matched prefix of the extracted address.

Abstract: The inventive device comprises a hash operation means 11 for operating and outputting a hash value of inputted fixed length data, a data table memory 14 consisting of N numbers of memory banks, where N is an integer that is more than and equal to 2, the data table memory 14 for storing a data table holding a large number of fixed length data, a pointer table memory 13 for storing a memory pointer table holding a memory address at which each fixed length datum is stored with said hash value as an index, and a comparison means 15 for simultaneously comparing a plurality of fixed length data stored at the same memory address in said N numbers of memory banks with a single fixed length datum inputted to said hash operation means, the comparison means 15 for outputting results of the comparison.

Abstract: A DRAM and a method of accessing a DRAM capable of obtaining a high data rate in a random row access. By selecting one of a plurality of main word lines (14), eight sub-word lines (16) are selected from 512 sub-word lines (16), and one sub-word line (16) is selected by a sub-word line (16) selecting signal and an enable signal.

Abstract: Upon implementing a data registration into or a data retrieval from a data table (3) where first item data are registered along with corresponding second item data, there are used a first pointer table (1) where pointers to part of the registered data in the data table are registered in storage positions that are designated by hash values obtained by applying a first hash function (6) to the first item data of the part of the registered data, and a second pointer table (2) where pointers to the other registered data in the data table are registered in storage positions that are designated by hash values obtained by applying a second hash function (22) to the first item data of the other registered data.

Abstract: To provide a DRAM that reduces loss time of accesses at the time of refresh and performs refresh for any other bank in parallel with normal accesses and is able to be used just like SRAM. DRAM comprises: refresh directing means for directing execution of refresh; bank specifying means for specifying a bank address of the memory cells to be refreshed; addressing means for addressing a row address of the memory cells to be refreshed in the specified bank; and execution means for refreshing the memory cells of the row address addressed in the specified bank in response to the direction of execution of refresh from the refresh directing means.

Abstract: The present invention relates to a DRAM having a memory array that is divided into a plurality of memory blocks. A memory block having a long data retention time is selected from the plurality of memory blocks and a logical address is allocated to the selected memory block. The selected memory block is refreshed at longer time intervals compared to conventional DRAMs resulting in lower power consumption.

Abstract: A distributor and a search controller are added to the memory. A search is performed with an algorithm such as quick search by repeating reading of memory cells, comparing of the reading result, and narrowing down of entries to be compared based on the comparison result. Performing this sequential processing in the memory provides valid data in a bus time plus about half of a cycle time required in repeating reading a conventional memory. Then, the latter half of the cycle time can be used for comparison, as well as generation of the next memory cell address, so that the search can be finished in a bus time multiplied by the number of repetitions of reading the memory cells plus one bus time. As a result, a CAM function can be achieved that allows for more than tens of thousands of entry data items, the number of which is equal to the size of DRAM divided by the number of banks, rather than hundreds or thousands of entry data items as conventional CAM.

Abstract: The present invention discloses a method for data input/output for memory which minimizes losses of data interruption when switching between reading and writing. A method for data input/output comprises the steps of: holding predetermined data from memory array 12 upon m-th (m is integer) read command; outputting the predetermined data to common I/O 30 and holding new data from memory array 12 upon (m+1)-th read command; holding predetermined data from common I/O 30 upon n-th (n is integer) write command; and storing the predetermined data in memory array 12 and holding new data from common I/O 30 upon (n+1)-th write command.

Abstract: An SRAM which eliminates any seam in consecutive read/write data flows when the burst-length is short, thus making it possible to achieve a seamless access in the burst-mode against data of different row-addresses between banks. This operation enables the band-width of SDRAM to approximate the data transmission rate at the peak moment determined by the maximum frequency of the clock.