Patents by Inventor Shinya Arai

Shinya Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10854534
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
  • Patent number: 10842431
    Abstract: A mental illness determination device includes a face change information acquisition unit and a mental illness determination unit. The face change information acquisition unit is configured to acquire face change information indicating a time-series change in face data of a subject when emotional stimulation information for stimulating any sense or any combination of senses among an auditory sense, an olfactory sense, a gustatory sense, a tactile sense, and a somatic sensation of the subject to change emotion, and is divided into positive information for increasing comfort and negative information for decreasing comfort is provided to the subject. The mental illness determination unit is configured to determine a state of mental illness of the subject on the basis of the face change information.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: November 24, 2020
    Assignees: Daikin Industries, Ltd., Tokyo Institute of Technology, National University Corporation Tottori University
    Inventors: Junichiro Arai, Akira Matsubara, Takahiro Hirayama, Hideki Hashizume, Takashi Gotou, Yasunori Kotani, Yoshimi Ohgami, Taro Tomatsu, Koichi Kaneko, Katsutoshi Yokoyama, Hiroshi Matsumura, Shenghong Pu, Masashi Itakura, Hiroaki Ohdachi, Masaru Ueki, Shinya Masuda
  • Publication number: 20200337757
    Abstract: Provided are a device whereby, during process of a process target such as a cell or the like, localized process of a process part is possible without inflicting damage due to heat, and rejoining and regeneration may proceed readily subsequent to process, and whereby an injection substance may be introduced efficiently; and a device for generating bubbles containing a plasma. Through the use of a localized ablation device employing a bubble jetting member having a core formed from a conductive material, a shell part formed from an insulating material, covering the core and including a section extending from the tip of the core, and a space formed between the extended section of the shell part and the tip of the core, a process target can be treated in localized fashion and without inflicting damage.
    Type: Application
    Filed: May 27, 2020
    Publication date: October 29, 2020
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yoko YAMANISHI, Shinya SAKUMA, Hiroki KURIKI, Fumihito ARAI
  • Publication number: 20200343264
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
  • Publication number: 20200335517
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA
  • Patent number: 10804288
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinya Arai
  • Publication number: 20200295037
    Abstract: In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.
    Type: Application
    Filed: September 9, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Iijima, Masayoshi Tagami, Shinya Arai, Takahiro Tomimatsu
  • Publication number: 20200286990
    Abstract: A semiconductor device including a first chip and a second chip. The first chip includes: a first substrate; a first transistor that is provided on the first substrate; and a first pad that is provided above the first transistor and that is electrically connected to the first transistor. The second chip includes: a second pad that is provided on the first pad; a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.
    Type: Application
    Filed: July 12, 2019
    Publication date: September 10, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhiro UCHIYAMA, Shinya ARAI, Koichi SAKATA, Takahiro TOMIMATSU
  • Patent number: 10756104
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
  • Patent number: 10741583
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Shinya Arai, Masaki Tsuji, Hideaki Aochi, Hiroyasu Tanaka
  • Publication number: 20200235125
    Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
    Type: Application
    Filed: April 9, 2020
    Publication date: July 23, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Shinya ARAI
  • Patent number: 10718386
    Abstract: A basic pulse time setting section determines a basic pulse time for initial invalid stroke elimination by applying current values of oil temperature and throttle opening to the basic pulse time map. A subtraction time setting section determines a subtraction time by applying current values of oil temperature and clutch oil pressure to the subtraction time map. A pulse time determining section determines a predetermined initial invalid stroke elimination pulse time by subtracting the subtraction time from the basic pulse time. An initial invalid stroke elimination permission/inhibition determination section, at a starting timing of initial invalid stroke elimination, inhibits this-time initial invalid stroke elimination if the elapsed time from the execution timing of the preceding initial invalid stroke elimination is within the predetermined inhibition period.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 21, 2020
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Naoki Sakamoto, Shinya Nishiyama, Dai Arai
  • Patent number: 10716610
    Abstract: Provided are a device whereby, during process of a process target such as a cell or the like, localized process of a process part is possible without inflicting damage due to heat, and rejoining and regeneration may proceed readily subsequent to process, and whereby an injection substance may be introduced efficiently; and a device for generating bubbles containing a plasma. Through the use of a localized ablation device employing a bubble jetting member having a core formed from a conductive material, a shell part formed from an insulating material, covering the core and including a section extending from the tip of the core, and a space formed between the extended section of the shell part and the tip of the core, a process target can be treated in localized fashion and without inflicting damage.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: July 21, 2020
    Assignee: Japan Science and Technology Agency
    Inventors: Yoko Yamanishi, Shinya Sakuma, Hiroki Kuriki, Fumihito Arai
  • Publication number: 20200179918
    Abstract: A dispensing apparatus, a liquid dispensing method, and a cell dispensing method which can dispense liquid with very high accuracy. A dispensing apparatus includes a glass pipette, a tubular elastic member, a rod-shaped member, and a piezoelectric element actuator. A portion of the tubular elastic member located adjacent to a first open end thereof covers a portion of the glass pipette located adjacent to an opening portion thereof. A portion of the tubular elastic member located adjacent to a second open end thereof covers at least a forward end portion of the rod-shaped member. When the piezoelectric element actuator pushes the rod-shaped member toward the opening portion of the glass pipette, the tubular elastic member deforms such that the volume of the internal space of the tubular elastic member decreases.
    Type: Application
    Filed: June 19, 2018
    Publication date: June 11, 2020
    Applicant: NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY
    Inventors: Shinya SAKUMA, Yusuke KASAI, Fumihito ARAI
  • Patent number: 10669525
    Abstract: Means which enables preparation of a thick cell aggregate by a simple process without an operation of detaching and stacking of cells is disclosed. The method for preparing a three-dimensional cell aggregate by the present invention comprises: a cell encasing step of placing a cell suspension in a cell container; and a pressure application step of applying pressure to cells in the container. The cell encasing step and the pressure application step may be carried out a plurality of times. By the present invention, a thick, robust cell aggregate can be obtained by a simple operation of applying pressure to a cell suspension or a medium containing cells. Since the method does not require an operation of stacking a plurality of cell sheets, the cells are hardly damaged, and the conditions of the cells can be favorably maintained, so that the cells can be advantageously used as a tissue piece for transplantation.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: June 2, 2020
    Assignees: PUBLIC UNIVERSITY CORPORATION YOKOHAMA CITY UNIVERSITY, OSAKA UNIVERSITY, NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY
    Inventors: Utako Yokoyama, Yoshihiro Ishikawa, Makoto Kaneko, Shinya Sakuma, Fumihito Arai
  • Patent number: 10665598
    Abstract: A semiconductor memory device includes a substrate, a plurality of first electrode layers, a semiconductor layer, a plurality of second electrode layers, and a conductor. The plurality of first electrode layers are arranged to be separated from each other in a first direction above the substrate. The semiconductor layer extends through the plurality of first electrode layers in the first direction. The plurality of second electrode layers are arranged to be separated from each other in the first direction, arranged to be separated from the plurality of first electrode layers in a second direction crossing the first direction, and arranged at substantially the same levels as levels of the plurality of first electrode layers in the first direction. The conductor electrically connects the plurality of second electrode layers to each other. The plurality of second electrode layers are connected in parallel by the conductor.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 26, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Shinya Arai
  • Patent number: 10651199
    Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: May 12, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shinya Arai
  • Publication number: 20200144278
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
  • Publication number: 20200122996
    Abstract: A coffee machine 1 having a body part 3, a door 2 that is openably and closably supported by the body part 3 and a cup station at which a cup is placed, the coffee machine 1 supplying milk from a milk nozzle 25 a distal end of which is disposed above the cup, to the cup placed at the cup station, in which the coffee machine 1 includes a movable nozzle support unit 27 that supports the milk nozzle 25 and is disposed in the body part 3 so as to be movable between a first position at which the distal end of the milk nozzle 25 is above the cup while the door 2 is closed and a second position at which the distal end of the milk nozzle 25 is retracted from above the cup and a nozzle movement unit 50 that moves a pusher 52 so as to extend to and retract from the door 2. The pusher 52 is extended to push the movable nozzle support unit 27 and move the movable nozzle support unit 27 to a supply position.
    Type: Application
    Filed: April 23, 2018
    Publication date: April 23, 2020
    Inventors: Takao MATSUMOTO, Shinya ARAI
  • Patent number: D883459
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: May 5, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinya Ishihama, Takanori Ikegaya, Satoshi Arai